Balanced Inductor H-Tree for Powering Energy-Efficient SFQ Circuits

    公开(公告)号:US20230187801A1

    公开(公告)日:2023-06-15

    申请号:US17644453

    申请日:2021-12-15

    CPC classification number: H01P3/00

    Abstract: An embodiment of the invention may include a circuit structure. The circuit structure may include a wiring tree located between a feeding Josephson transmission line (FJTL) and a global bias line. The circuit may include the wiring tree having an H-tree structure, wherein each branch of the H-tree is connected by a current limiting junction of the FJTL, and wherein a single output port of the H-tree structure is connected to the global bias line. Another embodiment of the invention may include a circuit structure a circuit structure a plurality of feeding Josephson transmission lines (FJTLs) located between a feed line and a global bias line. The path of from the feed line through each FJTL and to the global bias line is substantially similar.

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