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公开(公告)号：US20140101629A1
公开(公告)日：2014-04-10
申请号：US14100553
申请日：2013-12-09
IPC分类号： G06F17/50
CPC分类号： G06F17/505
摘要： Some example embodiments include a computer-implemented method for designing an integrated circuit. The computer-implemented method includes receiving a hierarchical network design for the integrated circuit, wherein the hierarchical design comprises a number of components that are coupled together. The computer-implemented method includes detecting that a component of the number of components has at least one of failed timing and incomplete timing based on a problem that comprises at least one of a missing assertion, one or more missing latches, a source driver having an input source slew that is greater than a source slew limit threshold, and a sink having an input sink slew that is greater than a sink slew limit threshold. The computer-implemented method includes replacing the component with a different component that is independent of the problem and testing others components of the number of components based on the different component.
摘要翻译： 一些示例性实施例包括用于设计集成电路的计算机实现的方法。 计算机实现的方法包括接收集成电路的分层网络设计，其中分层设计包括耦合在一起的多个组件。 计算机实现的方法包括基于包括缺失断言，一个或多个缺失锁存器，源驱动程序中的至少一个的问题，检测组件数量的组件具有故障定时和不完整定时中的至少一个 输入源电压大于源极限极限阈值，以及具有大于漏极极限极限阈值的输入接收器的接收器。 计算机实现的方法包括使用独立于问题的不同组件替换组件，并且基于不同的组件测试组件数量的其他组件。
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公开(公告)号：US09038009B2
公开(公告)日：2015-05-19
申请号：US14100553
申请日：2013-12-09
IPC分类号： G06F17/50
CPC分类号： G06F17/505
摘要： Some example embodiments include a computer-implemented method for designing an integrated circuit. The computer-implemented method includes receiving a hierarchical network design for the integrated circuit, wherein the hierarchical design comprises a number of components that are coupled together. The computer-implemented method includes detecting that a component of the number of components has at least one of failed timing and incomplete timing based on a problem that comprises at least one of a missing assertion, one or more missing latches, a source driver having an input source slew that is greater than a source slew limit threshold, and a sink having an input sink slew that is greater than a sink slew limit threshold. The computer-implemented method includes replacing the component with a different component that is independent of the problem and testing others components of the number of components based on the different component.
摘要翻译： 一些示例性实施例包括用于设计集成电路的计算机实现的方法。 计算机实现的方法包括接收集成电路的分层网络设计，其中分层设计包括耦合在一起的多个组件。 计算机实现的方法包括基于包括缺失断言，一个或多个缺失锁存器，源驱动程序中的至少一个的问题，检测组件数量的组件具有故障定时和不完整定时中的至少一个 输入源电压大于源极限极限阈值，以及具有大于漏极极限极限阈值的输入接收器的接收器。 计算机实现的方法包括使用独立于问题的不同组件替换组件，并且基于不同的组件测试组件数量的其他组件。
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公开(公告)号：US09092591B2
公开(公告)日：2015-07-28
申请号：US14249765
申请日：2014-04-10
发明人： Charles J. Alpert , Robert M. Averill, III , Eric J. Fluhr , Zhuo Li , Tuhin Mahmud , Jose L. P. Neves , Stephen T. Quay , Chin Ngai Sze , Yaoguang Wei
IPC分类号： G06F17/50
CPC分类号： G06F17/5077 , G06F17/505
摘要： Mechanisms are provided for pruning a layer trait library for use in wire routing in an integrated circuit design process. The mechanisms receive a plurality of wirecodes and a metal stack definition. The mechanisms generate a verbose layer trait library based on all possible combinations of the wirecodes and layers of the metal stack definition. The mechanisms generate a pruned layer trait library by pruning the verbose layer trait library to remove redundant layer traits from the verbose layer trait library. In addition, the mechanisms store the pruned layer trait library for performing wire routing of an integrated circuit design.
摘要翻译： 提供了用于在集成电路设计过程中修剪用于线路布线的层特征库的机制。 这些机构接收多个线编码和金属叠层定义。 这些机制基于金属堆栈定义的线代码和层的所有可能的组合来生成详细层特征库。 这些机制通过修剪详细图层特征库来从详细图层特征库中删除冗余图层特征来生成修剪图层特征库。 此外，机制存储用于执行集成电路设计的线路路由的修剪层特征库。
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公开(公告)号：US08769468B1
公开(公告)日：2014-07-01
申请号：US13737231
申请日：2013-01-09
发明人： Charles J. Alpert , Robert M. Averill, III , Eric J. Fluhr , Zhuo Li , Tuhin Mahmud , Jose L. P. Neves , Stephen T. Quay , Chin Ngai Sze , Yaoguang Wei
IPC分类号： G06F17/50
CPC分类号： G06F17/5077 , G06F17/505
摘要： Mechanisms are provided for pruning a layer trait library for use in wire routing in an integrated circuit design process. The mechanisms receive a plurality of wirecodes and a metal stack definition. The mechanisms generate a verbose layer trait library based on all possible combinations of the wirecodes and layers of the metal stack definition. The mechanisms generate a pruned layer trait library by pruning the verbose layer trait library to remove redundant layer traits from the verbose layer trait library. In addition, the mechanisms store the pruned layer trait library for performing wire routing of an integrated circuit design.
摘要翻译： 提供了用于在集成电路设计过程中修剪用于线路布线的层特征库的机制。 这些机构接收多个线编码和金属叠层定义。 这些机制基于金属堆栈定义的线代码和层的所有可能的组合来生成详细层特征库。 这些机制通过修剪详细图层特征库来从详细图层特征库中删除冗余图层特征来生成修剪图层特征库。 此外，机制存储用于执行集成电路设计的线路路由的修剪层特征库。
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