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公开(公告)号：US08930873B1
公开(公告)日：2015-01-06
申请号：US14081563
申请日：2013-11-15
发明人： Charles Jay Alpert , Zhuo Li , Gi-Joon Nam , Sven Peyer , Sourav Saha , Chin Ngai Sze , Yaoguang Wei
IPC分类号： G06F17/50
CPC分类号： G06F17/5081 , G06F17/5072 , G06F17/5077
摘要： A region of congestion is detected at a set of layers. The region occupies the same area of each layer in the set. A routing blockage is defined as a tuple corresponding to the region. The tuple includes a set of coordinates to describe an area of the region, a first and a second layer coordinates of a first and a second layer in the set of layers. The routing blockage is applied during an iteration of rough routing. Before an iteration of detailed routing, the routing blockage is removed. Detailed routing is performed using a g-cell in the region. The detailed routing uses a routing capacity saved in the g-cell during the iteration of rough routing due to the routing blockage. A revised IC design is produced where a revised congestion in an area corresponding to the region is reduced.
摘要翻译： 在一组层上检测到拥塞区域。 该区域占据集合中每层的相同区域。 路由阻塞被定义为对应于该区域的元组。 元组包括一组坐标以描述该区域的区域，该层集合中第一层和第二层的第一层和第二层坐标。 路由阻塞在粗略路由迭代过程中被应用。 在详细路由迭代之前，路由阻塞被删除。 使用该区域中的g-单元执行详细路由。 由于路由阻塞，详细路由使用在粗略路由迭代期间保存在g-cell中的路由容量。 产生了修改后的IC设计，其中与该区域对应的区域中的修改的拥塞减少。
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公开(公告)号：US08892344B2
公开(公告)日：2014-11-18
申请号：US14089860
申请日：2013-11-26
发明人： Charles Jay Alpert , Zhuo Li , Chin Ngai Sze , Yaoguang Wei
CPC分类号： G08G9/00 , G08G1/0104
摘要： A method, system, and computer program product for solving a traffic congestion problem are provided in the illustrative embodiments. Using an application executing using a processor and a memory in a data processing system, a congested route section is selected from a set of congested route sections. A set of congesting vehicles is selected, where the set of congesting vehicles cause congestion in the selected congested route sections by being positioned on the selected congested route section. A vacancy data structure corresponding to the selected congested route section is populated. A subset of the set of the congesting vehicles is selected. The subset of the set of the congesting vehicles is rerouted to a candidate route section identified in the vacancy data structure.
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公开(公告)号：US20140143746A1
公开(公告)日：2014-05-22
申请号：US13680775
申请日：2012-11-19
发明人： Charles Jay Alpert , Joseph Nicolas Kozhaya , Zhuo Li , Joseph J. Palumbo , Haifeng Qian , Phillip John Restle , Chin Ngai Sze , Ying Zhou
IPC分类号： G06F17/50
CPC分类号： G06F17/509 , G06F17/5036 , G06F2217/62
摘要： A design tool with a direct current (DC) transformation analysis unit determines combinations of candidate sink locations for sector buffers within a sector of a clock network design. For each of the combination of candidate sink locations, the design tool transforms resistances of the sector with the combination of candidate sink locations into resistances of an electrical circuit. The design tool transforms capacitances of the sector with the combination of candidate sink locations into current sources of an electrical circuit. The design tool performs a DC circuit analysis, wherein results of the DC circuit analysis include a variance of voltage at nodes of the sector and a maximum value of current from currents flowing between pairs of the nodes of the sector. The design tool determines which of the combination of candidate sink locations has the minimum variance of voltage with the results of the DC circuit analysis.
摘要翻译： 具有直流（DC）变换分析单元的设计工具确定时钟网络设计的扇区内扇区缓冲器的候选接收器位置的组合。 对于每个候选接收器位置的组合，设计工具将候选接收器位置的组合的扇区的电阻转换成电路的电阻。 设计工具通过候选接收器位置的组合将电路的电容转换为电路的电流源。 该设计工具执行直流电路分析，其中直流电路分析的结果包括扇区节点处的电压变化，以及来自在扇区对节点之间流动的电流的最大值。 设计工具确定候选接收器位置的哪一个组合具有电压的最小方差与直流电路分析的结果。
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公开(公告)号：US09038009B2
公开(公告)日：2015-05-19
申请号：US14100553
申请日：2013-12-09
IPC分类号： G06F17/50
CPC分类号： G06F17/505
摘要： Some example embodiments include a computer-implemented method for designing an integrated circuit. The computer-implemented method includes receiving a hierarchical network design for the integrated circuit, wherein the hierarchical design comprises a number of components that are coupled together. The computer-implemented method includes detecting that a component of the number of components has at least one of failed timing and incomplete timing based on a problem that comprises at least one of a missing assertion, one or more missing latches, a source driver having an input source slew that is greater than a source slew limit threshold, and a sink having an input sink slew that is greater than a sink slew limit threshold. The computer-implemented method includes replacing the component with a different component that is independent of the problem and testing others components of the number of components based on the different component.
摘要翻译： 一些示例性实施例包括用于设计集成电路的计算机实现的方法。 计算机实现的方法包括接收集成电路的分层网络设计，其中分层设计包括耦合在一起的多个组件。 计算机实现的方法包括基于包括缺失断言，一个或多个缺失锁存器，源驱动程序中的至少一个的问题，检测组件数量的组件具有故障定时和不完整定时中的至少一个 输入源电压大于源极限极限阈值，以及具有大于漏极极限极限阈值的输入接收器的接收器。 计算机实现的方法包括使用独立于问题的不同组件替换组件，并且基于不同的组件测试组件数量的其他组件。
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公开(公告)号：US08897998B2
公开(公告)日：2014-11-25
申请号：US14089892
申请日：2013-11-26
发明人： Charles Jay Alpert , Zhuo Li , Chin Ngai Sze , Yaoguang Wei
CPC分类号： G08G9/00 , G08G1/0104
摘要： A method, system, and computer program product for solving a traffic congestion problem are provided in the illustrative embodiments. Using an application executing using a processor and a memory in a data processing system, a congested route section is selected from a set of congested route sections. A set of congesting vehicles is selected, where the set of congesting vehicles cause congestion in the selected congested route sections by being positioned on the selected congested route section. A vacancy data structure corresponding to the selected congested route section is populated. A subset of the set of the congesting vehicles is selected. The subset of the set of the congesting vehicles is rerouted to a candidate route section identified in the vacancy data structure.
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公开(公告)号：US08881089B1
公开(公告)日：2014-11-04
申请号：US14108786
申请日：2013-12-17
发明人： Charles Jay Alpert , Glenn R. Bee , Zhuo Li , Tuhin Mahmud , Stephen T. Quay , Lakshmi N. Reddy , Chin Ngai Sze , Yaoguang Wei
IPC分类号： G06F17/50
CPC分类号： G06F17/5068
摘要： A system, process, etc. according to some embodiments, which includes operations that include selecting one of a plurality of solutions (“selected solution”) for optimization of an integrated circuit design during physical synthesis. The operations can further include performing on the selected solution a fast evaluation of a specific metric without updating design documents (e.g., without updating a netlist or metric map). If the evaluation of the specific metric is non-satisfactory, then the candidate solution is rejected. If the evaluation of the specific metric is satisfactory, then a design document is updated and a full evaluation of the specific metric (and other metrics) can be performed.
摘要翻译： 根据一些实施例的系统，过程等，其包括在物理合成期间包括选择多个解决方案之一（“选择的解决方案”）以优化集成电路设计的操作。 这些操作可以进一步包括在所选解决方案上执行特定度量的快速评估，而不更新设计文档（例如，不更新网表或度量图）。 如果对特定指标的评估不令人满意，则候选解决方案被拒绝。 如果对特定度量的评估是令人满意的，则设计文档被更新，并且可以执行特定度量（和其他度量）的全面评估。
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7.发明申请DETERMINING HIGH QUALITY INITIAL CANDIDATE SINK LOCATIONS FOR ROBUST CLOCK NETWORK DESIGN 审中-公开确定高质量的初始化候选网络位置，用于稳定的时钟网络设计公开(公告)号：US20140181772A1
公开(公告)日：2014-06-26
申请号：US13724212
申请日：2012-12-21
发明人： Charles Jay Alpert , Zhuo Li , Chin Ngai Sze , Ying Zhou
IPC分类号： G06F17/50
CPC分类号： G06F17/5077 , G06F2217/62
摘要： A design tool with an initial sink locator unit determines a number of clock buffers for driving clock signals to loads in a clock distribution network. The design tool determines clusters of loads in the clock distribution network, wherein the number of clusters is equal to the number of clock buffers and the loads are uniformly distributed amongst the clusters. The design tool determines centers of the clusters as initial candidate sink locations for the clock buffers. The design tool iteratively determines new clusters and determines centers of the new clusters as optimized initial candidate sink locations.
摘要翻译： 具有初始接收器定位器单元的设计工具确定用于将时钟信号驱动到时钟分配网络中的负载的多个时钟缓冲器。 设计工具确定时钟分配网络中的负载集群，其中集群的数量等于时钟缓冲器的数量，并且负载均匀分布在集群之间。 设计工具将集群的中心确定为时钟缓冲区的初始候选接收器位置。 设计工具迭代确定新的集群，并将新集群的中心确定为优化的初始候选接收器位置。
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公开(公告)号：US20140081478A1
公开(公告)日：2014-03-20
申请号：US14089892
申请日：2013-11-26
发明人： Charles Jay Alpert , Zhuo Li , Chin Ngai Sze , Yaoguang Wei
IPC分类号： G08G9/00
CPC分类号： G08G9/00 , G08G1/0104
摘要： A method, system, and computer program product for solving a traffic congestion problem are provided in the illustrative embodiments. Using an application executing using a processor and a memory in a data processing system, a congested route section is selected from a set of congested route sections. A set of congesting vehicles is selected, where the set of congesting vehicles cause congestion in the selected congested route sections by being positioned on the selected congested route section. A vacancy data structure corresponding to the selected congested route section is populated. A subset of the set of the congesting vehicles is selected. The subset of the set of the congesting vehicles is rerouted to a candidate route section identified in the vacancy data structure.
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公开(公告)号：US08775996B2
公开(公告)日：2014-07-08
申请号：US13680775
申请日：2012-11-19
发明人： Charles Jay Alpert , Joseph Nicolas Kozhaya , Zhuo Li , Joseph J. Palumbo , Haifeng Qian , Phillip John Restle , Chin Ngai Sze , Ying Zhou
IPC分类号： G06F17/50
CPC分类号： G06F17/509 , G06F17/5036 , G06F2217/62
摘要： A design tool with a direct current (DC) transformation analysis unit determines combinations of candidate sink locations for sector buffers within a sector of a clock network design. For each of the combination of candidate sink locations, the design tool transforms resistances of the sector with the combination of candidate sink locations into resistances of an electrical circuit. The design tool transforms capacitances of the sector with the combination of candidate sink locations into current sources of an electrical circuit. The design tool performs a DC circuit analysis, wherein results of the DC circuit analysis include a variance of voltage at nodes of the sector and a maximum value of current from currents flowing between pairs of the nodes of the sector. The design tool determines which of the combination of candidate sink locations has the minimum variance of voltage with the results of the DC circuit analysis.
摘要翻译： 具有直流（DC）变换分析单元的设计工具确定时钟网络设计的扇区内扇区缓冲器的候选接收器位置的组合。 对于每个候选接收器位置的组合，设计工具将候选接收器位置的组合的扇区的电阻转换成电路的电阻。 设计工具通过候选接收器位置的组合将电路的电容转换为电路的电流源。 该设计工具执行直流电路分析，其中直流电路分析的结果包括扇区节点处的电压方差和来自扇区对节点之间流动的电流的最大值。 设计工具确定候选接收器位置的哪一个组合具有电压的最小方差与直流电路分析的结果。
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公开(公告)号：US20140101629A1
公开(公告)日：2014-04-10
申请号：US14100553
申请日：2013-12-09
IPC分类号： G06F17/50
CPC分类号： G06F17/505
摘要： Some example embodiments include a computer-implemented method for designing an integrated circuit. The computer-implemented method includes receiving a hierarchical network design for the integrated circuit, wherein the hierarchical design comprises a number of components that are coupled together. The computer-implemented method includes detecting that a component of the number of components has at least one of failed timing and incomplete timing based on a problem that comprises at least one of a missing assertion, one or more missing latches, a source driver having an input source slew that is greater than a source slew limit threshold, and a sink having an input sink slew that is greater than a sink slew limit threshold. The computer-implemented method includes replacing the component with a different component that is independent of the problem and testing others components of the number of components based on the different component.
摘要翻译： 一些示例性实施例包括用于设计集成电路的计算机实现的方法。 计算机实现的方法包括接收集成电路的分层网络设计，其中分层设计包括耦合在一起的多个组件。 计算机实现的方法包括基于包括缺失断言，一个或多个缺失锁存器，源驱动程序中的至少一个的问题，检测组件数量的组件具有故障定时和不完整定时中的至少一个 输入源电压大于源极限极限阈值，以及具有大于漏极极限极限阈值的输入接收器的接收器。 计算机实现的方法包括使用独立于问题的不同组件替换组件，并且基于不同的组件测试组件数量的其他组件。
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