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    DATA FILTERING USING A PLURALITY OF HARDWARE ACCELERATORS
    3.
    发明申请
    DATA FILTERING USING A PLURALITY OF HARDWARE ACCELERATORS 审中-公开

    公开(公告)号：US20190266149A1

    公开(公告)日：2019-08-29

    申请号：US16412626

    申请日：2019-05-15

    申请人： International Business Machines Corporation

    发明人： Sameh Asaad ,  Robert J. Halstead ,  Bharat Sukhwani

    IPC分类号： G06F16/23 ,  G06F16/2455 ,  G06F16/245

    摘要： Techniques are provided for data filtering using hardware accelerators. An apparatus comprises a processor, a memory and a plurality of hardware accelerators. The processor is configured to stream data from the memory to a first one of the hardware accelerators and to receive filtered data from a second one of the hardware accelerators. The plurality of hardware accelerators are configured to filter the streamed data utilizing at least one bit vector partitioned across the plurality of hardware accelerators. The hardware accelerators may be field-programmable gate arrays.

    DATA FILTERING USING A PLURALITY OF HARDWARE ACCELERATORS
    6.
    发明申请
    DATA FILTERING USING A PLURALITY OF HARDWARE ACCELERATORS 审中-公开
    数据过滤使用多种硬件加速器

    公开(公告)号：US20160292201A1

    公开(公告)日：2016-10-06

    申请号：US14672630

    申请日：2015-03-30

    申请人： International Business Machines Corporation

    发明人： Sameh W. Asaad ,  Robert J. Halstead ,  Bharat Sukhwani

    IPC分类号： G06F17/30

    CPC分类号： G06F16/2365 ,  G06F16/24554 ,  G06F16/24569

    摘要： Techniques are provided for data filtering using hardware accelerators. An apparatus comprises a processor, a memory and a plurality of hardware accelerators. The processor is configured to stream data from the memory to a first one of the hardware accelerators and to receive filtered data from a second one of the hardware accelerators. The plurality of hardware accelerators are configured to filter the streamed data utilizing at least one bit vector partitioned across the plurality of hardware accelerators. The hardware accelerators may be field-programmable gate arrays.

    摘要翻译： 提供了使用硬件加速器进行数据过滤的技术。 一种装置包括处理器，存储器和多个硬件加速器。 处理器被配置为将数据从存储器流传输到硬件加速器中的第一个，并从第二个硬件加速器接收经滤波的数据。 多个硬件加速器被配置为利用在多个硬件加速器上划分的至少一个位向量来过滤流传输的数据。 硬件加速器可以是现场可编程门阵列。