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公开(公告)号：US20210240899A1
公开(公告)日：2021-08-05
申请号：US16779179
申请日：2020-01-31
发明人： Dongbing Shao , Rasit Onur Topaloglu , Geng Han , Yuping Cui
IPC分类号： G06F30/392 , G06F30/398
摘要： Aspects of the invention provide means for addressing layout retargeting shortfalls. Initially, an original design shape in the layout is allowed to be simulated by process simulation to form process simulation contours. A polygon is then fitted to the process simulation contours to form a fitted simulated shape. Subsequently, whether the fitted simulated shape differs from the original design shape is detected. The process simulation may reflect the changes to the layout that occur at a foundry as part of a retargeting process. Advantageously, addressing a layout for retargeting shortfalls in accordance with aspects of the invention is likely to result in manufactured semiconductor devices having higher yields and reliability than those produced from a like layout that is not addressed in this manner.
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公开(公告)号：US11574103B2
公开(公告)日：2023-02-07
申请号：US16779179
申请日：2020-01-31
发明人： Dongbing Shao , Rasit Onur Topaloglu , Geng Han , Yuping Cui
IPC分类号： G06F30/392 , G06F30/398 , G06F119/18
摘要： Aspects of the invention provide means for addressing layout retargeting shortfalls. Initially, an original design shape in the layout is allowed to be simulated by process simulation to form process simulation contours. A polygon is then fitted to the process simulation contours to form a fitted simulated shape. Subsequently, whether the fitted simulated shape differs from the original design shape is detected. The process simulation may reflect the changes to the layout that occur at a foundry as part of a retargeting process. Advantageously, addressing a layout for retargeting shortfalls in accordance with aspects of the invention is likely to result in manufactured semiconductor devices having higher yields and reliability than those produced from a like layout that is not addressed in this manner.
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