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公开(公告)号：US11812671B2
公开(公告)日：2023-11-07
申请号：US17068324
申请日：2020-10-12
CPC分类号： H10N60/0884 , G06N10/00 , H10N60/0912 , H10N60/12 , H10N60/805 , H10N69/00
摘要： Systems and techniques facilitating antenna-based thermal annealing of qubits are provided. In one example, a radio frequency emitter, transmitter, and/or antenna can be positioned above a superconducting qubit chip having a Josephson junction coupled to a set of one or more capacitor pads. The radio frequency emitter, transmitter, and/or antenna can emit an electromagnetic signal onto the set of one or more capacitor pads. The capacitor pads can function as receiving antennas and therefore receive the electromagnetic signal. Upon receipt of the electromagnetic signal, an alternating current and/or voltage can be induced in the capacitor pads, which current and/or voltage thereby heat the pads and the Josephson junction. The heating of the Josephson junction can change its physical properties, thereby annealing the Josephson junction. In another example, the emitter can direct the electromagnetic signal to avoid unwanted annealing of neighboring qubits on the superconducting qubit chip.
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公开(公告)号：US20220181154A1
公开(公告)日：2022-06-09
申请号：US17677469
申请日：2022-02-22
发明人： Rasit Onur Topaloglu , Kafai Lai , Dongbing Shao , Zheng Xu
IPC分类号： H01L21/033 , H01L23/528 , H01L21/768 , H01L21/311
摘要： A method of forming a semiconductor structure includes forming a dielectric layer, forming a plurality of mandrel lines over the dielectric layer, and forming a plurality of non-mandrel lines over the dielectric layer between adjacent ones of the mandrel lines utilizing self-aligned double patterning. The method also includes forming at least one spacer-merge region extending from a first portion of a first one of the mandrel lines to a second portion of a second one of the mandrel lines in a first direction and covering at least a portion of one or more of the non-mandrel lines between the first mandrel and the second mandrel in a second direction orthogonal to the first direction. The method further includes forming a plurality of trenches in the dielectric layer by transferring a pattern of (i) the mandrel lines and (ii) portions of the non-mandrel lines outside the at least one spacer-merge region.
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公开(公告)号：US20210280633A1
公开(公告)日：2021-09-09
申请号：US16808991
申请日：2020-03-04
摘要： Devices, systems, and/or methods that can facilitate local heating of a superconducting flux biasing loop are provided. According to an embodiment, a device can comprise a substrate having a superconducting flux bias circuit comprising a biasing loop coupled to a flux controlled qubit device. The device can further comprise a heating device coupled to the biasing loop.
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公开(公告)号：US20210240899A1
公开(公告)日：2021-08-05
申请号：US16779179
申请日：2020-01-31
发明人： Dongbing Shao , Rasit Onur Topaloglu , Geng Han , Yuping Cui
IPC分类号： G06F30/392 , G06F30/398
摘要： Aspects of the invention provide means for addressing layout retargeting shortfalls. Initially, an original design shape in the layout is allowed to be simulated by process simulation to form process simulation contours. A polygon is then fitted to the process simulation contours to form a fitted simulated shape. Subsequently, whether the fitted simulated shape differs from the original design shape is detected. The process simulation may reflect the changes to the layout that occur at a foundry as part of a retargeting process. Advantageously, addressing a layout for retargeting shortfalls in accordance with aspects of the invention is likely to result in manufactured semiconductor devices having higher yields and reliability than those produced from a like layout that is not addressed in this manner.
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公开(公告)号：US10714672B2
公开(公告)日：2020-07-14
申请号：US16248141
申请日：2019-01-15
IPC分类号： H01L39/24 , H01L39/22 , H01L27/18 , G06N10/00 , B82Y10/00 , B82Y40/00 , H01L39/02 , H01L29/66
摘要： Techniques for a vertical transmon qubit device are provided. In one embodiment, a chip surface base device structure is provided that comprises a first superconducting material physically coupled to a crystalline substrate, wherein the crystalline substrate is physically coupled to a second superconducting material, wherein the second superconducting material is physically coupled to a second crystalline substrate. In one implementation, the chip surface base device structure also comprises a vertical Josephson junction located in a via of the crystalline substrate, the vertical Josephson junction comprising the first superconducting material, a tunnel barrier, and the second superconducting material. In one implementation, the chip surface base device structure also comprises a transmon qubit comprising the vertical Josephson junction and a capacitor formed between the first superconducting material and the second superconducting material.
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公开(公告)号：US11700777B2
公开(公告)日：2023-07-11
申请号：US17021585
申请日：2020-09-15
IPC分类号： H01L29/66 , H10N69/00 , H10N60/01 , G01R33/035 , H03K19/195 , H10N60/12 , H10N60/80
CPC分类号： H10N69/00 , H10N60/0912 , G01R33/0354 , H03K19/195 , H10N60/12 , H10N60/805
摘要： Techniques related to vertical silicon-on-metal superconducting quantum interference devices and method of fabricating the same are provided. Also provided are associated flux control and biasing circuitry. A superconductor structure can comprise a silicon-on-metal substrate that can comprise a first superconducting layer, comprising a first superconducting material, between a first crystalline silicon layer and a second crystalline silicon layer. The superconducting structure can also comprise a first via comprising a first Josephson junction and a second via comprising a second Josephson junction. The first via and the second via can be formed between the first superconducting layer and a second superconducting layer, comprising a second superconducting material. An electrical loop around a defined area of the second crystalline silicon layer can comprise the first via comprising the first Josephson junction, the second via comprising the second Josephson junction, the first superconducting layer, and the second superconducting layer.
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公开(公告)号：US11482657B2
公开(公告)日：2022-10-25
申请号：US16676598
申请日：2019-11-07
摘要： Systems and techniques providing suitable chip structures for facilitating antenna-based thermal annealing of qubits are provided. In one example, a radio frequency emitter can comprise a voltage-controlled oscillator and an antenna. The voltage-controlled oscillator can receive power-on signals from a microcontroller, thereby causing the voltage-controlled oscillator to generate an electromagnetic wave. The antenna can then direct the electromagnetic wave onto a set of one or more capacitor pads of a Josephson junction on a superconducting qubit chip, thereby annealing the Josephson junction. In another example, a voltage regulator and a digital-to-analog converter or digital-to-digital converter can be coupled in series between the microcontroller and the voltage-controlled oscillator, thereby allowing the voltage-controlled oscillator to be voltage and/or frequency tunable and eliminating the need for external power routing as compared to photonic laser annealing. In yet another example, a bipolar-junction and complementary metal-oxide semiconductor stack construction can be employed.
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公开(公告)号：US20210234087A1
公开(公告)日：2021-07-29
申请号：US17230607
申请日：2021-04-14
摘要： Systems, computer-implemented methods, and techniques facilitating antenna-based thermal annealing of qubits are provided. In one example, a first antenna can be positioned above a superconducting qubit chip having a first Josephson junction and a second Josephson junction. The first antenna can direct a first electromagnetic wave toward the first Josephson junction. A first length of a first defined vertical gap, between the first antenna and the superconducting qubit chip, can be sized to cause the first electromagnetic wave to circumscribe a first set of one or more capacitor pads of the first Josephson junction, thereby annealing the first Josephson junction, without annealing the second Josephson junction. In another example, the first length of the first defined vertical gap can be a function of a model of the first electromagnetic wave as a cone, wherein the cone originates from the first antenna and extends toward the superconducting qubit chip.
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公开(公告)号：US10784432B2
公开(公告)日：2020-09-22
申请号：US16246676
申请日：2019-01-14
IPC分类号： H01L39/22 , H01L39/24 , H03K19/195 , H01L39/12 , B82Y10/00 , H01L27/18 , H01L39/02 , B82Y40/00 , G06N10/00
摘要： Techniques for a vertical Josephson junction superconducting device are provided. In one embodiment, a chip surface base device structure is provided that comprises a substrate comprising crystalline silicon that is coupled with a first superconducting layer, wherein the first superconducting layer is coupled with a second substrate comprising crystalline silicon. In one implementation, the chip surface base device structure also comprises a vertical Josephson junction located in an etched region of the substrate, the vertical Josephson junction comprising a first superconducting layer, a tunnel barrier layer, and a top superconducting layer.
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公开(公告)号：US10707402B2
公开(公告)日：2020-07-07
申请号：US16591993
申请日：2019-10-03
摘要： Systems and techniques facilitating antenna-based thermal annealing of qubits are provided. In one example, a radio frequency emitter, transmitter, and/or antenna can be positioned above a superconducting qubit chip having a Josephson junction coupled to a set of one or more capacitor pads. The radio frequency emitter, transmitter, and/or antenna can emit an electromagnetic signal onto the set of one or more capacitor pads. The capacitor pads can function as receiving antennas and therefore receive the electromagnetic signal. Upon receipt of the electromagnetic signal, an alternating current and/or voltage can be induced in the capacitor pads, which current and/or voltage thereby heat the pads and the Josephson junction. The heating of the Josephson junction can change its physical properties, thereby annealing the Josephson junction. In another example, the emitter can direct the electromagnetic signal to avoid unwanted annealing of neighboring qubits on the superconducting qubit chip.
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