公开(公告)号：US06693905B1

公开(公告)日：2004-02-17

申请号：US09541726

申请日：2000-04-03

申请人： Isamu Ishimura ,  Hiroshi Yoshida ,  Yoshihiro Tabira ,  Hirotaka Ito

发明人： Isamu Ishimura ,  Hiroshi Yoshida ,  Yoshihiro Tabira ,  Hirotaka Ito

IPC分类号： H04L1256

CPC分类号： H04L12/40071 ,  H04L1/1835 ,  H04L1/1874 ,  H04L12/40123 ,  H04L12/6418 ,  H04L47/2441 ,  H04L49/90 ,  H04L49/9089

摘要： A reception buffer, a transmission buffer, a transmission-reception buffer, a reception filter, a transmission filter and a packet processor are provided. If a response packet paired with a request packet has been received during a data exchange operation, then the reception filter stores the response packet received on the transmission-reception buffer and informs the packet processor of response detected. Alternatively, if a packet that has nothing to do with the current data exchange operation has been received, then the reception filter stores the received packet on the reception buffer and issues a suspension instruction to the packet processor. And when a transaction being carried out at the time of reception is completed, the packet processor suspends the data exchange. In this manner, the overheads involved with firmware processing by a central processing unit can be reduced and data can be exchanged at higher speeds.

公开(公告)号：US07127530B2

公开(公告)日：2006-10-24

申请号：US10124265

申请日：2002-04-18

申请人： Isamu Ishimura ,  Yoshihiro Tabira

发明人： Isamu Ishimura ,  Yoshihiro Tabira

IPC分类号： G06F13/38 ,  G06F13/00 ,  G06F3/00

CPC分类号： G06F13/126

摘要： In order to reduce load placed on a CPU (central processing unit) in providing SBP-2 (serial bus protocol 2) initiator capability, provided are a sequence control circuit activated by the CPU for controlling a command issue sequence, a packet processing circuit for assembling operation request blocks (ORB) into a transmission packet and extracting a status from a received packet; buffer for storing a command ORB provided by the CPU; a buffer for storing a management ORB provided by the CPU; a buffer for storing a status received for an issued management ORB and providing the status to the CPU; and a buffer for command for storing a status received for an issued command ORB and providing the status to the CPU.

公开(公告)号：US06654380B1

公开(公告)日：2003-11-25

申请号：US09497194

申请日：2000-02-03

申请人： Takashi Yumiba ,  Yoshihiro Tabira ,  Hirotaka Itoh ,  Isamu Ishimura

发明人： Takashi Yumiba ,  Yoshihiro Tabira ,  Hirotaka Itoh ,  Isamu Ishimura

IPC分类号： H04L2900

CPC分类号： H04L49/90 ,  H04L69/22

摘要： Reception buffer, transmission buffer, transmission-reception buffer, reception filter and transmission filter are provided. The reception filter determines where a received packet should be stored based on the contents of the received packet. Specifically, in executing a READ command, a response packet, which is returned in response to a data transmission packet, is detected by the reception filter. Received packets of the other types are stored on the reception buffer. In executing a WRITE command, a data request packet is transmitted from the transmission buffer. A data reception packet responding to the data request packet is stored by the reception filter on the transmission-reception buffer. Received packets of the other types are stored on the reception buffer. The capacity of the transmission-reception buffer is twice as large as the size of a maximum transferable packet. Thus, overhead can be reduced and yet data can be transferred at higher speeds.

摘要翻译： 提供接收缓冲器，发送缓冲器，发送接收缓冲器，接收滤波器和发送滤波器。 接收过滤器基于接收到的分组的内容来确定应该存储接收分组的位置。 具体地，在执行READ命令时，接收过滤器检测响应于数据传输分组返回的响应分组。 接收到的其他类型的数据包被存储在接收缓冲器中。 在执行WRITE命令时，从发送缓冲器发送数据请求分组。 响应于数据请求分组的数据接收分组由接收滤波器存储在发送接收缓冲器上。 接收到的其他类型的数据包被存储在接收缓冲器中。 发送接收缓冲器的容量是最大可传输分组的大小的两倍。 因此，可以降低开销，并且可以以更高的速度传输数据。

公开(公告)号：US06915359B2

公开(公告)日：2005-07-05

申请号：US09989302

申请日：2001-11-21

申请人： Youichi Yamamoto ,  Yoshihiro Tabira ,  Isamu Ishimura

发明人： Youichi Yamamoto ,  Yoshihiro Tabira ,  Isamu Ishimura

IPC分类号： G06F13/42 ,  G06F13/00 ,  G06F3/00

CPC分类号： G06F13/426

摘要： A data transfer device which set an address of page as transfer destination and transfer data to the page. In the data transfer device to which the present invention is applied, an address and page length of a page are acquired on the basis of an address of a page table specified by a read command. Then, transfer information including the address of transfer source, transfer data length and address of transfer destination of data is set according to page element of page as transfer destination page. Then, it is judged whether the transfer destination page and other page form a continuous area. And if it is judged that the continuous area is formed, transfer information will be changed. Data transfer is effected on the basis of changed transfer information. That reduces the need to set the other area at the transfer destination and thus the transfer efficiency improves.

摘要翻译： 数据传送装置，其将页面的地址设置为传送目的地并将数据传送到页面。 在应用本发明的数据传送装置中，基于由读取指令指定的页面表的地址来获取页面的地址和页面长度。 然后，根据页面页面作为传送目的地页面，设置包括传送源地址，传送数据长度和数据传送目的地地址的传送信息。 然后，判断转印目的地页面和其他页面是否形成连续区域。 并且如果判断出连续区域形成，则传送信息将被改变。 数据传输是根据改变的传输信息进行的。 这减少了在传送目的地设置其他区域的需要，从而提高了传输效率。

公开(公告)号：US20070180336A1

公开(公告)日：2007-08-02

申请号：US11640868

申请日：2006-12-19

申请人： Hirotaka Ito ,  Yoshihiro Tabira

发明人： Hirotaka Ito ,  Yoshihiro Tabira

IPC分类号： G06F11/00

CPC分类号： H04L12/40071 ,  H04L12/6418 ,  H04L69/22

摘要： The multi-initiator control unit for performing packet-unit communication with each of a plurality of devices connected via a transmission line includes: a packet filter for analyzing a received packet and outputting the results; a plurality of command control circuits each for controlling a command processing sequence performed with the corresponding device; a multi-control circuit for giving sequence execution permission to one of the plurality of command control circuits; and a packet processing circuit for generating a packet containing information output by the permission-given command control circuit and outputting the packet for transmission, and also outputting a received packet according to the analysis results output by the packet filter.

摘要翻译： 用于通过传输线连接的多个设备中的每一个进行分组单元通信的多发起者控制单元包括：分组过滤器，用于分析接收的分组并输出结果; 多个命令控制电路，用于控制与相应装置执行的命令处理顺序; 用于向所述多个命令控制电路之一提供序列执行许可的多控制电路; 以及分组处理电路，用于生成包含由许可命令控制电路输出的信息的分组并输出用于传输的分组，并且还根据分组过滤器输出的分析结果输出接收的分组。

公开(公告)号：US07164689B2

公开(公告)日：2007-01-16

申请号：US09998693

申请日：2001-12-03

申请人： Hirotaka Ito ,  Yoshihiro Tabira

发明人： Hirotaka Ito ,  Yoshihiro Tabira

IPC分类号： H04L12/28

CPC分类号： H04L12/40071 ,  H04L12/6418 ,  H04L69/22

摘要： The multi-initiator control unit for performing packet-unit communication with each of a plurality of devices connected via a transmission line includes: a packet filter for analyzing a received packet and outputting the results; a plurality of command control circuits each for controlling a command processing sequence performed with the corresponding device; a multi-control circuit for giving sequence execution permission to one of the plurality of command control circuits; and a packet processing circuit for generating a packet containing information output by the permission-given command control circuit and outputting the packet for transmission, and also outputting a received packet according to the analysis results output by the packet filter.

公开(公告)号：US06977901B2

公开(公告)日：2005-12-20

申请号：US09838181

申请日：2001-04-20

申请人： Hirotaka Ito ,  Yoshihiro Tabira

发明人： Hirotaka Ito ,  Yoshihiro Tabira

IPC分类号： H04L29/06 ,  H04L12/40 ,  H04L12/64 ,  H04L29/08 ,  H04L12/28 ,  G06F15/16 ,  H04L12/56

CPC分类号： H04L12/40071 ,  H04L12/64

摘要： If a packet processing controller at a consumer node has failed to process a received packet within a predetermined amount of time, a packet processing control timer detects a time-out and informs a CPU of that. In response, the CPU issues packet processing suspend instruction and packet transmit instruction for the controller by way of a register. In accordance with these instructions, the controller suspends the current packet processing and produces header and data for a WRS packet, which is transmitted to a producer node through a bus. In this manner, a packet can be processed without causing a time-out at the producer node.

摘要翻译： 如果消费者节点处的分组处理控制器在预定时间量内未能处理接收到的分组，则分组处理控制定时器检测到超时并通知CPU。 作为响应，CPU通过寄存器向控制器发出数据包处理挂起指令和数据包发送指令。 根据这些指令，控制器暂停当前分组处理，并产生用于通过总线传送到生产者节点的WRS分组的报头和数据。 以这种方式，可以处理分组而不会在生成器节点处造成超时。

公开(公告)号：US5396129A

公开(公告)日：1995-03-07

申请号：US66225

申请日：1993-05-25

申请人： Yoshihiro Tabira

发明人： Yoshihiro Tabira

IPC分类号： H03K5/15 ,  H03K19/003 ,  H03K19/096

CPC分类号： H03K19/00323 ,  H03K5/15066

摘要： In a semiconductor integrated circuit apparatus, a first logic circuit processes a clock signal inputted through an external clock input terminal, and each of a plurality of second logic circuits processes the clock signal outputted from the first logic circuit, and outputs the processed clock signal to a plurality of flip-flops. In the semiconductor integrated circuit apparatus, an inner clock signal line is provided for electrically connecting the plurality of second logic circuits with the plurality of flip-flops, wherein the inner clock signal line is formed in a ring shape in the periphery of the semiconductor integrated circuit apparatus so that the plurality of flip-flops are located within the inner clock signal line, thereby reducing the clock skews therebetween in the semiconductor integrated circuit. Furthermore, an outer clock signal line is provided for electrically connecting the first logic circuit with the plurality of second logic circuits, and then the outer clock signal line is formed in a ring shape, thereby further reducing the clock skews therebetween in the semiconductor integrated circuit.

摘要翻译： 在半导体集成电路装置中，第一逻辑电路处理通过外部时钟输入端子输入的时钟信号，并且多个第二逻辑电路中的每一个处理从第一逻辑电路输出的时钟信号，并将处理的时钟信号输出到 多个触发器。 在半导体集成电路装置中，提供内部时钟信号线，用于将多个第二逻辑电路与多个触发器电连接，其中内部时钟信号线在半导体集成的外围形成为环形 电路装置，使得多个触发器位于内部时钟信号线内，从而减少半导体集成电路中的时钟偏差。 此外，提供外部时钟信号线用于将第一逻辑电路与多个第二逻辑电路电连接，然后外部时钟信号线形成为环形形状，从而进一步减小半导体集成电路中的时钟偏差 。

公开(公告)号：US07565473B2

公开(公告)日：2009-07-21

申请号：US11403807

申请日：2006-04-14

申请人： Yoshihiro Tabira ,  Satoshi Takahashi

发明人： Yoshihiro Tabira ,  Satoshi Takahashi

IPC分类号： H05K7/10

CPC分类号： G06F13/4081 ,  Y02D10/14 ,  Y02D10/151

摘要： In a semiconductor integrated circuit, a detection confirmation circuit sets the logical level of a second signal according to the logical level of a first signal observed after a lapse of a predetermined time since detection of insertion/removal of a cable for peripheral equipment. The semiconductor integrated circuit operates in a standby mode in which only the insertion/removal detection circuit operates if no cable for peripheral equipment is connected, in a repeater mode in which only PHY operates if a cable for peripheral equipment is connected and CPU is in the suspended state, and in a normal mode in which both PHY and LINK operate if a cable for peripheral equipment is connected and a CPU is in the operating state.

摘要翻译： 在半导体集成电路中，检测确认电路根据从检测到用于外围设备的电缆的插入/拔出之后经过预定时间后观察到的第一信号的逻辑电平来设置第二信号的逻辑电平。 半导体集成电路在待机模式下工作，其中仅在没有连接用于外围设备的电缆的情况下仅在连接了用于外围设备的电缆的CPU的中继器模式中才插入/移除检测电路，并且CPU处于 并且在正常模式下，如果连接了用于外围设备的电缆，并且CPU处于工作状态，PHY和LINK两者都将工作。

公开(公告)号：US20060236009A1

公开(公告)日：2006-10-19

申请号：US11400531

申请日：2006-04-10

申请人： Yoshihiro Tabira

发明人： Yoshihiro Tabira

IPC分类号： G06F13/00

CPC分类号： G06F13/28 ,  G06F12/1081 ,  G06F13/385

摘要： A data transmitter includes a bus master circuit. The bus master circuit obtains the right to use a CPU bus and directly performs data transmission to and from a working memory connected to the CPU bus through a CPU interface section and the CPU bus.

摘要翻译： 数据发送器包括总线主电路。 总线主电路获得使用CPU总线的权利，并通过CPU接口部分和CPU总线直接执行连接到CPU总线的工作内存的数据传输。