公开(公告)号：US5598105A

公开(公告)日：1997-01-28

申请号：US562746

申请日：1995-11-27

申请人： Itaru Kurosawa ,  Hiroshi Nakagawa ,  Masahiro Aoyagi ,  Masaaki Maezawa ,  Takashi Nanya ,  Yoshio Kameda

发明人： Itaru Kurosawa ,  Hiroshi Nakagawa ,  Masahiro Aoyagi ,  Masaaki Maezawa ,  Takashi Nanya ,  Yoshio Kameda

IPC分类号： H01L39/22 ,  H03K19/195

CPC分类号： H03K19/1954

摘要： An elementary cell uses single-flux-quanta as two-valued logic propagation signals and is effective for Constructing asynchronous superconducting logic circuits. The elementary cell comprises one OR circuit section and one AND circuit section. Input pulses applied to two input terminals of the elementary cell are split at signal splitting sections in the elementary cell and applied to both inputs of the OR circuit section and both inputs of the AND circuit section. The output of the OR circuit section is defined as the OR output of the elementary cell. A first arrival pulse memory section is provided in the AND circuit section and when one of two input pulses input to the two input terminals of the AND circuit section arrives before the other, this fact is recorded in the first arrival pulse memory section as logical "1". When the other input pulse arrives while logical "1" is recorded in the first arrival pulse memory section, the AND circuit section produces an AND output which is defined as the AND output of the elementary cell. When a reset signal pulse is applied to a reset terminal, the first arrival pulse memory section is reset.

摘要翻译： 基本单元使用单通量量子作为二值逻辑传播信号，对于构造异步超导逻辑电路是有效的。 基本单元包括一个OR电路部分和一个AND电路部分。 施加到基本单元的两个输入端子的输入脉冲在基本单元中的信号分离部分处被分离，并且被施加到“或”电路部分的两个输入端和“与”电路部分的两个输入端。 OR电路部分的输出被定义为基本单元的OR输出。 在AND电路部分中设置第一到达脉冲存储器部分，并且当输入到AND电路部分的两个输入端子的两个输入脉冲之一到达另一个时，该事实被记录在第一到达脉冲存储器部分中作为逻辑“ 1“。 当在第一到达脉冲存储器部分中记录逻辑“1”时另一个输入脉冲到达时，与电路部分产生被定义为基本单元的与输出的“与”输出。 当将复位信号脉冲施加到复位端子时，第一到达脉冲存储器部分被复位。