公开(公告)号：US5325341A

公开(公告)日：1994-06-28

申请号：US936989

申请日：1992-08-31

申请人： J. Greg Viot ,  Robert J. Amedeo ,  Nancy L. Thomas ,  Marc L. DeWever ,  Dale J. Kumke ,  Everett R. Lumpkin

发明人： J. Greg Viot ,  Robert J. Amedeo ,  Nancy L. Thomas ,  Marc L. DeWever ,  Dale J. Kumke ,  Everett R. Lumpkin

IPC分类号： G04F10/04 ,  G04F8/00 ,  G06F1/04

CPC分类号： G04F10/04

摘要： A digital timer apparatus incorporates a free running counter, an interval timer, a capture register, a pulse accumulator; holding logic and mode selection logic. In one mode of operation, a rising or falling edge of an external signal causes the current contents of the free running counter to be loaded into the capture register, causes the previous value of the capture register to be transferred to a holding register and causes the pulse accumulator to be incremented. A read of the capture holding register causes the pulse accumulator value to be transferred to a holding register and causes the pulse accumulator to be reset. The output of the interval timer can cause an interrupt signal to be generated to request service from a central processing unit. The timer apparatus is particularly well suited to performing tasks related to the determination of the speed of rotation of a rotating member and may be used, for instance, in detecting wheel rotational speeds in an anti-lock brake system or detecting shaft rotation speeds in an automatic transmission.

摘要翻译： 数字定时器装置包括自由运行计数器，间隔定时器，捕获寄存器，脉冲累加器; 保持逻辑和模式选择逻辑。 在一种操作模式中，外部信号的上升或下降沿使自由运行计数器的当前内容加载到捕捉寄存器中，使得捕获寄存器的先前值被传送到保持寄存器，并导致 脉冲累加器增加。 捕获保持寄存器的读取将脉冲累加器值传送到保持寄存器，并使脉冲累加器复位。 间隔定时器的输出可以产生中断信号以从中央处理单元请求服务。 定时器装置特别适合于执行与确定旋转部件的旋转速度有关的任务，并且可以用于例如在防抱死制动系统中检测轮转速或检测轴转速 自动变速器。