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公开(公告)号：US20200044632A1
公开(公告)日：2020-02-06
申请号：US16051102
申请日：2018-07-31
IPC分类号： H03K3/38 , H03K19/195 , G11C11/44 , H03K19/20
摘要： A reciprocal quantum logic (RQL) phase-mode D flip-flop accepts a data input and a logical clock input. A D flip-flop with an enable input further accepts enable input and further requires that the enable be asserted high to allow the data input to change the output on the logical clock pulse. The flip-flop includes a storage loop and a comparator, each of which includes Josephson junctions (JJs). The storage loop stores the data input, provided as a positive or negative single flux quantum (SFQ) pulse, is stored in the storage loop as positive or negative state, respectively, effectively biasing a JJ shared between the storage loop and the comparator. The data input is captured to the output upon clocking (or enabled clocking), when a clock pulse causes the shared JJ to preferentially trigger over an escape JJ in the comparator, the shared JJ having been biased by storage loop current.
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公开(公告)号：US20190238137A1
公开(公告)日：2019-08-01
申请号：US16102385
申请日：2018-08-13
IPC分类号： H03K19/195 , G06N10/00 , B82Y10/00 , H03M7/00 , H03K19/177 , G11C11/44 , H01L39/02
CPC分类号： H03K19/195 , B82Y10/00 , G06N10/00 , G11C11/44 , H01L39/025 , H03K19/17708 , H03K19/1952 , H03K19/1954 , H03M7/003
摘要： Superconducting methods of determining AND, OR, AND-OR, and OR-AND logic values use single flux quantum (SFQ) pulses to assert logical inputs of a reciprocal quantum logic (RQL) gate by placing currents in input storage loops in the RQL gate and, based on the currents in the storage loops, triggering logical decision Josephson junctions (JJs) in the gate, such that an assertion or de-assertion signal corresponding to the logical function of the gate is observed at the output. The methods permit for outputs based on at least four logical inputs to be achieved.
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