公开(公告)号：US12094530B2

公开(公告)日：2024-09-17

申请号：US17815358

申请日：2022-07-27

Applicant: IMEC VZW

Inventor： Henry Luo ,  Anna Yurievna Herr ,  Quentin Paul Herr

IPC: G11C11/44

CPC classification number: G11C11/44

Abstract: Josephson junction based memory devices and methods for their use are described herein. An example Josephson junction based memory device includes a plurality of superconducting loops. Each superconducting loop includes at least one Josephson junction. The plurality of superconducting loops are electrically coupled. The plurality of superconducting loops include a plurality of input loops, a plurality of readout loops, and at least one shared loop. The plurality of superconducting loops are configured to store or annihilate magnetic flux quanta in one or more of the superconducting loops in response to a combination of control signals and single flux quantum (SFQ) pulses.

公开(公告)号：US11991935B2

公开(公告)日：2024-05-21

申请号：US17990864

申请日：2022-11-21

Applicant: SeeQC Inc.

Inventor： Daniel Yohannes ,  Mario Renzullo ,  John Vivalda ,  Alexander Kirichenko

IPC: G11C16/04 ,  G11C11/44 ,  H10N60/12 ,  H10N60/80 ,  H10N60/84 ,  H10N69/00

CPC classification number: H10N60/84 ,  G11C11/44 ,  H10N60/12 ,  H10N60/805 ,  H10N69/00

Abstract: Materials and methods are disclosed for fabricating superconducting integrated circuits for quantum computing at millikelvin temperatures, comprising both quantum circuits and classical control circuits, which may be located on the same integrated circuit or on different chips of a multi-chip module. The materials may include components that reduce defect densities and increase quantum coherence times. Multilayer fabrication techniques provide low-power and a path to large scale computing systems. An integrated circuit system for quantum computing is provided, comprising: a substrate; a kinetic inductance layer having a kinetic inductance of at least 5 pH/square; a plurality of stacked planarized superconducting layers and intervening insulating layers, formed into a plurality of Josephson junctions having a critical current of less than 100 μA/μm2; and a resistive layer that remains non-superconducting at a temperature below 1 K, configured to damp the plurality of Josephson junctions.

公开(公告)号：US20240005986A1

公开(公告)日：2024-01-04

申请号：US17993586

申请日：2022-11-23

Applicant: William Robert Reohr

Inventor： William Robert Reohr

IPC: G11C11/44 ,  G11C7/12 ,  H03K3/38 ,  H03K19/195

CPC classification number: G11C11/44 ,  G11C7/12 ,  H03K3/38 ,  H03K19/1952

Abstract: A superconducting distributed bidirectional current driver system includes multiple bidirectional current drivers, a bidirectional current load being operatively coupled between two adjacent bidirectional current drivers. Each of the bidirectional current drivers includes first and second superconducting latch circuits. The first superconducting latch circuit in a first one of the bidirectional current drivers and the second superconducting latch circuit in a second one of the bidirectional current drivers coupled to the current load are selectively activated by first and second activation signals, respectively, to establish a first current path through the current load in a first direction. The second superconducting latch circuit in the second one of the bidirectional current drivers and the first superconducting latch circuit in the first one of the bidirectional current drivers are selectively activated to establish a second current path through the current load in a second direction opposite the first direction.

公开(公告)号：US20240005968A1

公开(公告)日：2024-01-04

申请号：US17993543

申请日：2022-11-23

Applicant: William Robert Reohr ,  Benjamin Bogan Reohr

Inventor： William Robert Reohr ,  Benjamin Bogan Reohr

IPC: G11C7/10 ,  G11C11/44

CPC classification number: G11C7/1066 ,  G11C7/1063 ,  G11C7/1096 ,  G11C11/44

Abstract: A memory output circuit for selectively propagating proximate memory output data in a memory array of superconducting memory cells includes multiple datum inputs adapted to operably receive corresponding memory state signals from physically adjacent bit lines in the memory array, and at least one logic gate configured to implement logical OR functionality. The logic gate includes multiple inputs, for receiving at least a subset of the datum inputs operatively coupled thereto, and an output for propagating at least one datum output signal. The memory output circuit further includes at least one delay element operatively coupled to a corresponding one of the datum inputs. The delay element is configured to generate an output signal operably connected to a corresponding one of the inputs of the logic gate, the output signal generated by the delay element being a temporal sequence of at least a subset of the memory state signals supplied thereto delayed by a prescribed delay value.

公开(公告)号：US11831313B2

公开(公告)日：2023-11-28

申请号：US18046757

申请日：2022-10-14

Applicant: Microsoft Technology Licensing, LLC

Inventor： Kushal Das ,  Alireza Moini ,  David J. Reilly

IPC: H03K19/195 ,  H02M1/08 ,  G06N10/00 ,  G06F9/448 ,  G06F1/03 ,  G06F9/30 ,  G11C11/44 ,  H02M3/07 ,  H10B63/00 ,  H04L45/00 ,  H04L1/24 ,  H04L7/033

CPC classification number: H03K19/1958 ,  G06F1/0321 ,  G06F9/30098 ,  G06F9/4498 ,  G06N10/00 ,  G11C11/44 ,  H02M1/08 ,  H02M3/07 ,  H03K19/195 ,  H04L1/24 ,  H04L7/033 ,  H04L45/40 ,  H10B63/30

Abstract: Systems and methods related to charge locking circuits and a control system for qubits are provided. A system for controlling qubit gates includes a first packaged device comprising a quantum device including a plurality of qubit gates, where the quantum device is configured to operate at a cryogenic temperature. The system further includes a second packaged device comprising a control circuit configured to operate at the cryogenic temperature, where the first packaged device is coupled to the second packaged device, and where the control circuit comprises a plurality of charge locking circuits, where each of the plurality of charge locking circuits is coupled to at least one qubit gate of the plurality of qubit gates via an interconnect such that each of the plurality of charge locking circuits is configured to provide a voltage signal to at least one qubit gate.

公开(公告)号：US11823736B1

公开(公告)日：2023-11-21

申请号：US17683219

申请日：2022-02-28

Applicant: SeeQC Inc.

Inventor： Oleg Mukhanov ,  Alan M. Kadin ,  Ivan P. Nevirkovets ,  Igor V. Vernik

IPC: G11C11/44 ,  G11C11/16 ,  H10N60/12 ,  H10N60/80 ,  H10N60/01

CPC classification number: G11C11/44 ,  G11C11/161 ,  G11C11/1659 ,  G11C11/1673 ,  G11C11/1675 ,  H10N60/0912 ,  H10N60/12 ,  H10N60/805 ,  Y10S505/832

Abstract: A superconducting memory cell includes a magnetic Josephson junction (MJJ) with a ferromagnetic material, having at least two switchable states of magnetization. The binary state of the MJJ manifests itself as a pulse appearing, or not appearing, on the output. A superconducting memory includes an array of memory cells. Each memory cell includes a comparator with at least one MJJ. Selected X and Y-directional write lines in their combination are capable of switching the magnetization of the MJJ. A superconducting device includes a first and a second junction in a stacked configuration. The first junction has an insulating layer barrier, and the second junction has an insulating layer sandwiched in-between two ferromagnetic layers as barrier. An electrical signal inputted across the first junction is amplified across the second junction.

公开(公告)号：US20230337553A1

公开(公告)日：2023-10-19

申请号：US17990864

申请日：2022-11-21

Applicant: SeeQC Inc.

Inventor： Daniel Yohannes ,  Mario Renzullo ,  John Vivalda ,  Alexander Kirichenko

IPC: G11C11/44

CPC classification number: H10N60/84 ,  H10N60/12 ,  H10N69/00 ,  G11C11/44 ,  H10N60/805

Abstract: Materials and methods are disclosed for fabricating superconducting integrated circuits for quantum computing at millikelvin temperatures, comprising both quantum circuits and classical control circuits, which may be located on the same integrated circuit or on different chips of a multi-chip module. The materials may include components that reduce defect densities and increase quantum coherence times. Multilayer fabrication techniques provide low-power and a path to large scale computing systems. An integrated circuit system for quantum computing is provided, comprising: a substrate; a kinetic inductance layer having a kinetic inductance of at least 5 pH/square; a plurality of stacked planarized superconducting layers and intervening insulating layers, formed into a plurality of Josephson junctions having a critical current of less than 100 μA/μm2; and a resistive layer that remains non-superconducting at a temperature below 1 K, configured to damp the plurality of Josephson junctions.

公开(公告)号：US20230197147A1

公开(公告)日：2023-06-22

申请号：US17554994

申请日：2021-12-17

Applicant: International Business Machines Corporation

Inventor： Takashi Imamichi ,  Naoki Kanazawa ,  Sami Rosenblatt ,  Benjamin Fearon

IPC: G11C11/44 ,  G06N10/40

CPC classification number: G11C11/44 ,  G06N10/40

Abstract: Systems and techniques that facilitate TLS-based optimization of Stark tone tuning are provided. In various embodiments, a system can comprise a receiver component that can access a qubit topology. In various aspects, the system can further comprise an optimization component that can identify, based on a set of two-level-system, (TLS) frequency regions of the qubit topology, one or more Stark tone frequencies. In various instances, the system can further comprise an execution component that can apply, to a qubit lattice corresponding to the qubit topology, one or more Stark tones that have the one or more Stark tone frequencies, thereby eliminating frequency collisions in the qubit lattice.

公开(公告)号：US20190188596A1

公开(公告)日：2019-06-20

申请号：US15774503

申请日：2016-11-10

Applicant: Engin Ipek ,  Ben Feinberg ,  Shibo Wang ,  Mahdi N. Bojnordi ,  Ravi Patel ,  Eby G. Friedman

Inventor： Engin Ipek ,  Ben Feinberg ,  Shibo Wang ,  Mahdi N. Bojnordi ,  Ravi Patel ,  Eby G. Friedman

IPC: G06N10/00 ,  G06F7/38 ,  G06F9/30 ,  H03K19/195 ,  G11C11/44 ,  G11C11/16 ,  G11C19/32

CPC classification number: G06N10/00 ,  G06F1/16 ,  G06F7/381 ,  G06F9/3004 ,  G06F9/30105 ,  G06F9/3016 ,  G11C11/161 ,  G11C11/1673 ,  G11C11/1675 ,  G11C11/44 ,  G11C19/32 ,  H01L27/18 ,  H01L27/222 ,  H01L39/223 ,  H01L43/02 ,  H03K19/195

Abstract: An energy efficient rapid single flux quantum (ERSFQ) logic register wheel includes a circular shift register having a plurality of destructive read out (DRO) cells. Each entry of the circular shift register includes a data block, a tag, and a valid bit. A compare and control logic is coupled to the circular shift register to compare a source specifier or a destination register specifier against a register tag stored in the wheel following each cycle of the register wheel. At least one or more read ports and at least one or more write ports are coupled to the circular shift register to write to or to read from a different entry each in the register wheel following each cycle of the register wheel. A RSFQ clearable FIFO with flushing and a crosspoint memory topology for integrating MRAM devices with ERSFQ circuits are also described.

公开(公告)号：US20180314970A1

公开(公告)日：2018-11-01

申请号：US16029040

申请日：2018-07-06

Applicant: D-Wave Systems Inc.

Inventor： Richard G. Harris ,  Mohammad H. Amin ,  Anatoly Smirnov

IPC: G06N99/00 ,  H03K19/195

CPC classification number: G06N99/002 ,  G11C11/44 ,  H03K3/38 ,  H03K19/1952

Abstract: A quantum processor is operable as a universal adiabatic quantum computing system. The quantum processor includes physical qubits, with at least a first and second communicative coupling available between pairs of qubits via an in-situ tunable superconducting capacitive coupler and an in-situ tunable superconducting inductive coupler, respectively. Tunable couplers provide diagonal and off-diagonal coupling. Compound Josephson junctions (CJJs) of the tunable couplers are responsive to a flux bias to tune a sign and magnitude of a sum of a capacitance of a fixed capacitor and a tunable capacitance which is mediated across a pair of coupling capacitors. The qubits may be hybrid qubits, operable in a flux regime or a charge regime. Qubits may include a pair of CJJs that interrupt a loop of material and which are separated by an island of superconducting material which is voltage biased with respect to a qubit body.