公开(公告)号：US20220406370A1

公开(公告)日：2022-12-22

申请号：US17877452

申请日：2022-07-29

Applicant: JAPAN SCIENCE AND TECHNOLOGY AGENCY

Inventor： Satoshi Sugahara ,  Yusaku Shiotsu

IPC: G11C11/412 ,  G11C11/419 ,  H03K3/3565 ,  H01L27/11

Abstract: A bistable circuit includes a pair of inverter circuits each including a first FET being connected between a power supply line and an intermediate node and having a gate coupled to an input node and a first conductivity type channel, a second FET being connected between the intermediate node and an output node and having a gate coupled to the input node and the first conductivity type channel, a third FET being connected between the intermediate node and a bias node, a fourth FET being connected between the output node and a control line and having a gate coupled to a word line and a second conductivity type channel, wherein the pair of inverter circuits are connected in a loop shape, and gates of the third FETs of the pair of inverter circuits are coupled to one of the input and output nodes of the pair of inverter circuits.

公开(公告)号：US20250069651A1

公开(公告)日：2025-02-27

申请号：US18947451

申请日：2024-11-14

Applicant: JAPAN SCIENCE AND TECHNOLOGY AGENCY

Inventor： Satoshi Sugahara ,  Yusaku Shiotsu

IPC: G11C11/412 ,  G11C11/419 ,  H03K3/3565 ,  H10B10/00

Abstract: A bistable circuit includes a pair of inverter circuits each including a first FET being connected between a power supply line and an intermediate node and having a gate coupled to an input node and a first conductivity type channel, a second FET being connected between the intermediate node and an output node and having a gate coupled to the input node and the first conductivity type channel, a third FET being connected between the intermediate node and a bias node, a fourth FET being connected between the output node and a control line and having a gate coupled to a word line and a second conductivity type channel, wherein the pair of inverter circuits are connected in a loop shape, and gates of the third FETs of the pair of inverter circuits are coupled to one of the input and output nodes of the pair of inverter circuits.

公开(公告)号：US12183392B2

公开(公告)日：2024-12-31

申请号：US17877452

申请日：2022-07-29

Applicant: JAPAN SCIENCE AND TECHNOLOGY AGENCY

Inventor： Satoshi Sugahara ,  Yusaku Shiotsu

IPC: G11C11/00 ,  G11C11/412 ,  G11C11/419 ,  H03K3/3565 ,  H10B10/00

Abstract: A bistable circuit includes a pair of inverter circuits each including a first FET being connected between a power supply line and an intermediate node and having a gate coupled to an input node and a first conductivity type channel, a second FET being connected between the intermediate node and an output node and having a gate coupled to the input node and the first conductivity type channel, a third FET being connected between the intermediate node and a bias node, a fourth FET being connected between the output node and a control line and having a gate coupled to a word line and a second conductivity type channel, wherein the pair of inverter circuits are connected in a loop shape, and gates of the third FETs of the pair of inverter circuits are coupled to one of the input and output nodes of the pair of inverter circuits.