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1.发明申请METHOD AND SYSTEM FOR SCALABLE REDUCTION IN REGISTERS WITH SAT-BASED RESUBSTITUTION 失效用于基于SAT的调整的寄存器中可缩放的方法和系统公开(公告)号：US20120167024A1
公开(公告)日：2012-06-28
申请号：US13415924
申请日：2012-03-09
IPC分类号： G06F17/50
CPC分类号： G06F17/505
摘要： A method, system, and computer program product for reducing the size of a logic network design, prior to verification of the logic network design. The method includes eliminating registers to reduce the size of the logic network design; thereby, increasing the speed and functionality of the verification process, and decreasing the size of the logic network design. The system identifies one or more compatible resubstitutions of a selected register, wherein the compatible resubstitution expresses the selected register as one or more pre-existing registers of fixed initial state. The resubstitutions are refined utilizing design invariants. When one more resubstitutions are preformed, the system eliminates the selected registers to reduce the size of the logic network design. As a result of the resubstitution process, a logic network design of reduced size is generated.
摘要翻译： 在验证逻辑网络设计之前，用于减小逻辑网络设计大小的方法，系统和计算机程序产品。 该方法包括消除寄存器以减小逻辑网络设计的大小; 从而增加验证过程的速度和功能，并减小逻辑网络设计的大小。 系统识别所选择的寄存器的一个或多个兼容的重新配置，其中兼容重新配置将所选择的寄存器表示为一个或多个预先存在的固定初始状态的寄存器。 利用设计不变量来改进重组。 当再进行一次重新配置时，系统将删除所选择的寄存器以减小逻辑网络设计的大小。 作为重新配置处理的结果，生成尺寸减小的逻辑网络设计。
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公开(公告)号：US20080228694A1
公开(公告)日：2008-09-18
申请号：US12129976
申请日：2008-05-30
IPC分类号： G06F17/30
CPC分类号： G06F17/504
摘要： A method for performing verification includes selecting a first set containing a seed register and adding to a second set a result of a subtraction of a fanout of the first set from a fanin of the first set. A third set is rendered equal to a result of a subtraction of a fanin of the second set from a fanout of the second set, and whether a combination of the first set and the third set is equivalent to the first set is determined. In response to determining that the combination of the first set and the second set is not equivalent to the first set, a min-cut of the first set and the second set containing a minimal set of predicates between a first component and the logic to which the component fans out, wherein the logic is bordered by the second set is returned.
摘要翻译： 一种用于执行验证的方法包括：选择包含种子寄存器的第一集合，并且从第一组的扇区中减去第一组的扇出结果，向第二组添加结果。 第三组被赋予等于从第二组的扇出中减去第二组的扇形的结果，以及第一组和第三组的组合是否等同于第一组的结果。 响应于确定第一集合和第二集合的组合不等同于第一集合，第一集合和第二集合的最小化包含第一组件和逻辑之间的最小一组谓词 组件风扇出来，其中返回逻辑与第二组相邻的逻辑。
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3.发明申请METHOD, SYSTEM AND APPLICATION FOR SEQUENTIAL COFACTOR-BASED ANALYSIS OF NETLISTS 有权方法，系统和应用程序，用于基于网格的基于配置因子的分析公开(公告)号：US20100251197A1
公开(公告)日：2010-09-30
申请号：US12410962
申请日：2009-03-25
IPC分类号： G06F17/50
CPC分类号： G06F17/5022
摘要： Methods, systems and computer products are provided for reducing the design size of an integrated circuit while preserving the behavior of the design with respect to verification results. A multiplexer is inserted at the gate being analyzed, and the multiplexer selector is controlled to provide a predetermined output for one frame at the point being analyzed. It is then determined whether the circuit remains equivalent during application of the predetermined output in order to decide whether the gate being analyzed is a candidate for replacement.
摘要翻译： 提供了方法，系统和计算机产品，用于减少集成电路的设计尺寸，同时保持设计相对于验证结果的行为。 在被分析的门处插入复用器，并且多路复用器选择器被控制以在被分析的点处为一帧提供预定的输出。 然后在应用预定输出期间确定电路是否保持等效，以便确定被分析的门是否是替换候选。
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公开(公告)号：US20080066033A1
公开(公告)日：2008-03-13
申请号：US11940711
申请日：2007-11-15
申请人： JASON BAUMGARTNER , ROBERT KANZELMAN , HARY MONY , VIRESH PARUTHI
发明人： JASON BAUMGARTNER , ROBERT KANZELMAN , HARY MONY , VIRESH PARUTHI
IPC分类号： G06F17/50
CPC分类号： G06F17/504
摘要： A method for performing verification is disclosed. The method includes selecting a first computer-design constraint for simplification and applying structural reparamaterization to simplify the first computer-design constraint. In response to determining that the first computer-design constraint is not eliminated, the first computer-design constraint is set equal to a dead-end state of the constraint. A structural preimage of the first computer-design constraint is created, in response to determining that a combination of a target and the dead-end state of the first computer-design constraint is equal to a combination of the target and the structural preimage of the first computer-design constraint, the first computer-design constraint is set equal to the structural preimage.
摘要翻译： 公开了一种用于执行验证的方法。 该方法包括选择第一计算机设计约束以简化并应用结构化重新定位以简化第一计算机设计约束。 响应于确定第一计算机设计约束不被消除，第一计算机设计约束被设置为等于约束的死端状态。 响应于确定第一计算机设计约束的目标和死端状态的组合等于目标和第一计算机设计约束的结构前图像的组合，创建第一计算机设计约束的结构预图像 第一个计算机设计约束，第一个计算机设计约束被设置为等于结构前像。
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