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1.发明授权公开(公告)号：US08589837B1
公开(公告)日：2013-11-19
申请号：US13455839
申请日：2012-04-25
IPC分类号： G06F17/50
CPC分类号： G06F17/505 , G06F17/504
摘要： A computer-implemented method simplifies a netlist, verifies the simplified netlist using induction, and remaps resulting inductive counterexamples via inductive trace lifting within a multi-algorithm verification framework. The method includes: a processor deriving a first unreachable state information that can be utilized to simplify the netlist; performing a simplification of the netlist utilizing the first unreachable state information; determining whether the first unreachable state information can be inductively proved on an original version of the netlist; and in response to the first unreachable state information not being inductively provable on the original netlist: projecting the first unreachable state information to a minimal subset; and adding the projected unreachable state information as an invariant to further constrain a child induction process. Adding the projected state information as an invariant ensures that any resulting induction counterexamples can be mapped to valid induction counterexamples on the original netlist before undergoing the simplification.
摘要翻译： 计算机实现的方法简化网表，使用归纳验证简化的网表，并通过多算法验证框架内的归纳跟踪提升重新生成归纳反例。 该方法包括：处理器导出可用于简化网表的第一不可达状态信息; 利用第一不可达状态信息来执行网表的简化; 确定在网表的原始版本上是否可以感应地证明第一不可达状态信息; 并且响应于在原始网表上不被感应地证明的第一不可达状态信息：将第一不可达状态信息投射到最小子集; 并且将预测的不可达状态信息添加为不变量以进一步约束儿童归纳过程。 将投影状态信息添加为不变量确保在进行简化之前，任何导致的归因反例可以映射到原始网表上的有效归纳反例。
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2.发明授权Minimizing memory array representations for enhanced synthesis and verification 有权最小化存储器阵列表示，以增强综合和验证公开(公告)号：US08307313B2
公开(公告)日：2012-11-06
申请号：US12775607
申请日：2010-05-07
CPC分类号： G06F17/505
摘要： Mechanisms are provided in a design environment for minimizing memory array representations for enhanced synthesis and verification. The design environment comprises one mechanism to compress the width of arrays using disconnected pin information. The design environment comprises another mechanism to simplify the enable conditions of array ports using “don't care” computations. The design environment comprises yet another mechanism to reduce address pins from an array through analysis of limitations of readable addresses.
摘要翻译： 在用于最小化存储器阵列表示以用于增强的合成和验证的设计环境中提供机制。 设计环境包括使用断开的引脚信息压缩阵列宽度的一种机制。 设计环境包括使用无关心计算简化阵列端口使能条件的另一种机制。 设计环境包括通过分析可读地址的限制来减少地址引脚从阵列的另一机制。
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3.发明授权Performing minimization of input count during structural netlist overapproximation 失效在结构化网表过度近似期间执行输入计数的最小化公开(公告)号：US08185852B2
公开(公告)日：2012-05-22
申请号：US12047361
申请日：2008-03-13
IPC分类号： G06F17/50
CPC分类号： G06F17/504
摘要： A method for performing verification is disclosed. The method includes selecting a set of gates to add to a first localization netlist and forming a refinement netlist. A min-cut is computed with sinks having one or more gates in the refinement netlist and sources comprising one or more inputs of an original netlist and one or more registers registers of the original netlist which are not part of the refinement netlist. A final localized netlist is obtained by adding one or more gates to the refinement netlist to grow the refinement netlist until reaching one or more cut-gates of the min-cut.
摘要翻译： 公开了一种用于执行验证的方法。 该方法包括选择一组门以添加到第一定位网表并形成细化网表。 使用在细化网表中具有一个或多个门的信宿和包括原始网表的一个或多个输入和不属于细化网表的原始网表的一个或多个寄存器寄存器的源来计算最小值。 通过将一个或多个门添加到细化网表来获得最终的本地化网表，以增加细化网表，直到达到最小切割的一个或多个切割点。
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公开(公告)号：US20120054701A1
公开(公告)日：2012-03-01
申请号：US12871962
申请日：2010-08-31
CPC分类号： G06F17/504
摘要： Mechanisms are provided for refining an abstraction of a netlist for verification or synthesis of an integrated circuit design. The mechanisms receive an abstracted netlist corresponding to an original netlist of the integrated circuit design. The mechanisms determine elements already present in the abstracted netlist and refine the abstracted netlist by expanding the abstracted netlist to include additional elements that are correlated with the elements already present in the abstracted netlist to thereby generate a refined abstracted netlist. In addition, the mechanisms utilize the refined abstracted netlist to perform at least one of verification or synthesis of the integrated circuit design.
摘要翻译： 提供了用于改进用于验证或综合集成电路设计的网表的抽象的机制。 这些机制接收到与集成电路设计的原始网表相对应的抽象网表。 这些机制确定已经存在于抽象网表中的元素，并通过扩展抽象网表来改进抽象网表，以包括与抽象网表中已经存在的元素相关联的附加元素，从而生成精简抽象网表。 另外，这些机制利用精简的抽象网表来执行集成电路设计的验证或合成中的至少一个。
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5.发明授权Method, system and application for sequential cofactor-based analysis of netlists 有权网表的顺序辅因子分析的方法，系统和应用公开(公告)号：US08042075B2
公开(公告)日：2011-10-18
申请号：US12410962
申请日：2009-03-25
CPC分类号： G06F17/5022
摘要： Methods, systems and computer products are provided for reducing the design size of an integrated circuit while preserving the behavior of the design with respect to verification results. A multiplexer is inserted at the gate being analyzed, and the multiplexer selector is controlled to provide a predetermined output for one frame at the point being analyzed. It is then determined whether the circuit remains equivalent during application of the predetermined output in order to decide whether the gate being analyzed is a candidate for replacement.
摘要翻译： 提供了方法，系统和计算机产品，用于减少集成电路的设计尺寸，同时保持设计相对于验证结果的行为。 在被分析的门处插入复用器，并且多路复用器选择器被控制以在被分析的点处为一帧提供预定的输出。 然后在应用预定输出期间确定电路是否保持等效，以便确定被分析的门是否是替换候选。
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6.发明授权Method and system for reduction of XOR/XNOR subexpressions in structural design representations 有权在结构设计表示中减少XOR / XNOR子表达式的方法和系统公开(公告)号：US07831937B2
公开(公告)日：2010-11-09
申请号：US11955112
申请日：2007-12-12
IPC分类号： G06F17/50
CPC分类号： G06F17/505
摘要： A method, system and computer program product for reducing XOR/XNOR subexpressions in structural design representations are disclosed. The method includes receiving an initial design, in which the initial design represents an electronic circuit containing an XOR gate. A first simplification mode for the initial design is selected from a set of applicable simplification modes, wherein the first simplification mode is an XOR/XNOR simplification mode, and a simplification of the initial design is performed according to the first simplification mode to generate a reduced design containing a reduced number of XOR gates. Whether a size of the reduced design is less than a size of the initial design is determined, and, in response to determining that the size of the reduced design is less than a the size of the initial design, the initial design is replaced with the reduced design.
摘要翻译： 公开了一种用于在结构设计表示中减少XOR / XNOR子表达式的方法，系统和计算机程序产品。 该方法包括接收初始设计，其中初始设计表示包含XOR门的电子电路。 从一组适用的简化模式中选择用于初始设计的第一简化模式，其中第一简化模式是XOR / XNOR简化模式，并且根据第一简化模式执行简化初始设计以生成缩减 设计包含减少数量的异或门。 确定缩减设计的尺寸是否小于初始设计的尺寸，并且响应于确定减小的设计的尺寸小于初始设计的尺寸，初始设计被替换为 减少设计。
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公开(公告)号：US07788616B2
公开(公告)日：2010-08-31
申请号：US11940755
申请日：2007-11-15
IPC分类号： G06F17/50
CPC分类号： G06F17/504
摘要： A method for performing verification is disclosed. The method includes selecting a first computer-design constraint for simplification and applying structural reparamaterization to simplify the first computer-design constraint. In response to determining that the first computer-design constraint is not eliminated, the first computer-design constraint is set equal to a dead-end state of the constraint. A structural preimage of the first computer-design constraint is created, in response to determining that a combination of a target and the dead-end state of the first computer-design constraint is equal to a combination of the target and the structural preimage of the first computer-design constraint, the first computer-design constraint is set equal to the structural preimage.
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8.发明申请Method and System for Sequential Netlist Reduction Through Trace-Containment 有权通过跟踪控制进行顺序网表减少的方法和系统公开(公告)号：US20100218148A1
公开(公告)日：2010-08-26
申请号：US12392278
申请日：2009-02-25
IPC分类号： G06F17/50
CPC分类号： G06F17/505 , G06F17/504
摘要： Methods and systems are provided for sequential netlist reduction through trace-containment for a circuitry design netlist by first identifying a cut of the netlist and enumerating a set of mismatch traces. Perform time-bounded unfolding of a cofactored version of the cut to reflect the sequential cofactor for a specific input i and temporal uncorrelation constraints for the set of inputs ‘J’. Determine whether there is trace containment by performing equivalence checking with respect to the cut of the netlist under temporal uncorrelation constraints for the set of inputs ‘J’. In response to detecting trace containment, simplify the netlist by merging the input ‘i’ to a constant.
摘要翻译： 提供方法和系统，用于通过电路设计网表的跟踪容纳来顺序的网表减少，首先识别网表的剪切并列举一组不匹配的跟踪。 执行切片的辅助版本的时间限制展开，以反映特定输入i的顺序辅因子和输入集合J'的时间非相关约束。 通过对输入集合J'的时间不相关约束执行相对于网表的切分的等价性检查来确定是否存在跟踪容纳。 响应检测跟踪容纳，通过将输入'i'合并为常数来简化网表。
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公开(公告)号：US07734452B2
公开(公告)日：2010-06-08
申请号：US11675698
申请日：2007-02-16
IPC分类号： G06F17/50
CPC分类号： G06F17/505 , G06F17/5022
摘要： A method and system for performing ternary verification is disclosed. Initially, a ternary model is generated from a binary model of a logic circuit design. The pairings used to encode the ternary model are then recorded. Next, the number of the recorded gate pairings is reduced by removing all invalid gate pairings. A ternary verification is performed on the ternary model having a reduced number of gate pairings.
摘要翻译： 公开了一种用于执行三元验证的方法和系统。 最初，从逻辑电路设计的二进制模型生成三元模型。 然后记录用于对三元模型进行编码的配对。 接下来，通过去除所有无效的门对配对来减少所记录的门对配对数。 对具有减少数量的门对配对的三元模型进行三进制验证。
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10.发明授权Method and system for enhanced verification by closely coupling a structural satisfiability solver and rewriting algorithms 失效通过紧密耦合结构可满足性求解器和重写算法来增强验证的方法和系统公开(公告)号：US07478344B2
公开(公告)日：2009-01-13
申请号：US11443906
申请日：2006-05-31
IPC分类号： G06F17/50
CPC分类号： A61F13/472 , A61F13/202 , A61F13/2051 , A61F13/206 , A61F13/2065 , A61F13/2068 , G06F8/72
摘要： A method, system and computer program product are disclosed. The method includes initializing a first variable to limit a rewrite time for rewrite operations with respect to an initial design by a rewriting module, a second variable to limit a time for satsifability solver operations with respect to said initial design by a staisfiability solver module and a third variable to limit a maximum number of rewrite iterations with respect to said initial design. A timer is called to track said rewrite time and a local logic rewriting operation is run on said initial design with said rewrite module. In response to determining that all of all targets for said initial design netlist are not solved, whether a rewrite time is expired is determined. In response to determining that said rewrite time is not expired, AND refactoring is run. In response to determining that said rewrite time is not expired, XOR refactoring is run.
摘要翻译： 公开了一种方法，系统和计算机程序产品。 该方法包括：初始化第一变量以限制由重写模块相对于初始设计的重写操作的重写时间;第二变量，用于限制由可靠性求解器模块相对于所述初始设计的可乘坐解算器操作的时间;以及 第三变量以限制相对于所述初始设计的最大重写迭代次数。 调用定时器以跟踪所述重写时间，并且利用所述重写模块在所述初始设计上运行本地逻辑重写操作。 响应于确定所有初始设计网表的所有目标未被解决，确定重写时间是否到期。 响应于确定所述重写时间未过期，并且运行重构。 响应于确定所述重写时间未过期，运行XOR重构。
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