公开(公告)号：US12118940B2

公开(公告)日：2024-10-15

申请号：US18334930

申请日：2023-06-14

Applicant: JOLED INC.

Inventor： Hiroshi Fujimura ,  Hitoshi Tsuge

IPC: G09G3/3233

CPC classification number: G09G3/3233 ,  G09G2300/0413 ,  G09G2300/0819 ,  G09G2300/0852 ,  G09G2320/0247

Abstract: A control method is a method of a display device including a plurality of pixel circuits. Each of the pixel circuits includes a light emitting element, a drive transistor, and a pixel capacitance. The drive transistor includes a gate and a source. A frame period includes a first subframe period and at least one second subframe period. In the first subframe period, the control method includes: (A) applying a first initialization potential to the source; (B) writing a signal into the pixel capacitance; and (C) causing the light emitting element to emit light. In each of the at least one second subframe period, the control method includes: (D) maintaining the light emitting element in a non-emission state; (E) applying a second initialization potential to the source in (D); and (F) causing the light emitting element to emit light.

公开(公告)号：US10431159B2

公开(公告)日：2019-10-01

申请号：US15232297

申请日：2016-08-09

Applicant: JOLED Inc.

Inventor： Hiroshi Fujimura

IPC: G09G3/3266

Abstract: A register circuit includes an output circuit and an input circuit. The output circuit includes a first transistor and a second transistor. The first transistor is provided in a first electrically-conductive path between a first control terminal and an output terminal. The second transistor is provided in a second electrically-conductive path between a first power terminal and the output terminal. The input circuit includes a third transistor and a fourth transistor. The third transistor is provided in a third electrically-conductive path between an input terminal and a gate terminal of the first transistor. The fourth transistor is provided in a fourth electrically-conductive path between a second control terminal and a gate terminal of the third transistor and has a gate terminal that is coupled to the input terminal.

公开(公告)号：US10176751B2

公开(公告)日：2019-01-08

申请号：US15863290

申请日：2018-01-05

Applicant: JOLED INC.

Inventor： Tetsuro Yamamoto ,  Hiroshi Fujimura

IPC: G09G3/3208

Abstract: A drive circuit having an output terminal includes a buffer circuit including a first transistor and a second transistor that are connected in parallel between a power supply and the output terminal. The first transistor and the second transistor are controlled such that after the first transistor and the second transistor are simultaneously turned on, the second transistor is turned off earlier than the first transistor.

公开(公告)号：US20170061879A1

公开(公告)日：2017-03-02

申请号：US15232297

申请日：2016-08-09

Applicant: JOLED Inc.

Inventor： Hiroshi Fujimura

IPC: G09G3/3233 ,  G09G3/3266

CPC classification number: G09G3/3266 ,  G09G2310/0286

Abstract: A register circuit includes an output circuit and an input circuit. The output circuit includes a first transistor and a second transistor. The first transistor is provided in a first electrically-conductive path between a first control terminal and an output terminal. The second transistor is provided in a second electrically-conductive path between a first power terminal and the output terminal. The input circuit includes a third transistor and a fourth transistor. The third transistor is provided in a third electrically-conductive path between an input terminal and a gate terminal of the first transistor. The fourth transistor is provided in a fourth electrically-conductive path between a second control terminal and a gate terminal of the third transistor and has a gate terminal that is coupled to the input terminal.

Abstract translation: 寄存器电路包括输出电路和输入电路。 输出电路包括第一晶体管和第二晶体管。 第一晶体管设置在第一控制端子和输出端子之间的第一导电路径中。 第二晶体管设置在第一电源端子和输出端子之间的第二导电路径中。 输入电路包括第三晶体管和第四晶体管。 第三晶体管设置在第一晶体管的输入端和栅极端之间的第三导电路径中。 第四晶体管设置在第三控制端子和第三晶体管的栅极端子之间的第四导电路径中，并且具有耦合到输入端子的栅极端子。

公开(公告)号：US09984627B2

公开(公告)日：2018-05-29

申请号：US15268839

申请日：2016-09-19

Applicant: JOLED Inc.

Inventor： Hiroshi Fujimura ,  Tetsuro Yamamoto

IPC: G06F1/00 ,  G09G3/3258 ,  G09G3/3266

CPC classification number: G09G3/3258 ,  G09G3/3233 ,  G09G3/3266 ,  G09G2300/0426 ,  G09G2300/043 ,  G09G2300/0452 ,  G09G2300/0842 ,  G09G2320/0233 ,  G09G2320/0247

Abstract: A display panel includes a plurality of pixels, and a plurality of signal lines and a plurality of power lines. The plurality of pixels are disposed in matrix. The plurality of signal lines and the plurality of power lines both extend in a column direction. The plurality of power lines include a plurality of first power lines assigned to respective odd-numbered pixel rows and a plurality of second power lines assigned to respective even-numbered pixel rows. The first power lines are electrically coupled to one another. The second power lines are electrically coupled to one another.

公开(公告)号：US20170092197A1

公开(公告)日：2017-03-30

申请号：US15268839

申请日：2016-09-19

Applicant: JOLED Inc.

Inventor： Hiroshi Fujimura ,  Tetsuro Yamamoto

IPC: G09G3/3258 ,  G09G3/3266

CPC classification number: G09G3/3258 ,  G09G3/3233 ,  G09G3/3266 ,  G09G2300/0426 ,  G09G2300/043 ,  G09G2300/0452 ,  G09G2300/0842 ,  G09G2320/0233 ,  G09G2320/0247

Abstract: A display panel includes a plurality of pixels, and a plurality of signal lines and a plurality of power lines. The plurality of pixels are disposed in matrix. The plurality of signal lines and the plurality of power lines both extend in a column direction. The plurality of power lines include a plurality of first power lines assigned to respective odd-numbered pixel rows and a plurality of second power lines assigned to respective even-numbered pixel rows. The first power lines are electrically coupled to one another. The second power lines are electrically coupled to one another.