公开(公告)号：US08407650B1

公开(公告)日：2013-03-26

申请号：US12129916

申请日：2008-05-30

申请人： Jacob Avidan ,  Sandeep Grover ,  Roger Carpenter ,  Philippe Sarrazin

发明人： Jacob Avidan ,  Sandeep Grover ,  Roger Carpenter ,  Philippe Sarrazin

IPC分类号： G06F17/50

CPC分类号： G06F17/5077

摘要： In various embodiments, each possible different instance of a repeated block can be concurrently modified for chip routing. Repeated blocks can be implemented where all instances of a repeated block are identical or substantially identical. Pin placement may be determined based on analysis of the I/O for all instances. The pin placement may be generated to be identical or substantially similar for all instances. Flyover blockages can be designed into repeated blocks to enable the global router to wire through the repeated block. Buffers and associated pins can be inserted into repeated block within the flyover space where the global router wires to the needed buffer through area pins.

摘要翻译： 在各种实施例中，重复块的每个可能的不同实例可以被同时修改用于芯片路由。 可以在重复块的所有实例相同或基本相同的情况下实现重复块。 可以基于对所有实例的I / O的分析来确定引脚放置。 针脚放置可以被生成为与所有实例相同或基本相似。 天桥拦截可以设计成重复的块，以使全局路由器能够穿过重复的块。 缓冲器和相关引脚可以插入飞越空间内的重复块，其中全局路由器通过区域引脚连接到所需的缓冲区。

公开(公告)号：US07971168B1

公开(公告)日：2011-06-28

申请号：US12128919

申请日：2008-05-29

申请人： Robert Swanson ,  Jacob Avidan ,  Roger Carpenter

发明人： Robert Swanson ,  Jacob Avidan ,  Roger Carpenter

IPC分类号： G06F17/50

CPC分类号： G06F17/5045

摘要： In various embodiments, each possible different instance of a repeated block can be concurrently optimized for timing. Each instance of a repeated block may be treated as a mode, such as a functional mode or testing mode, allowing implementation calculations to be performed simultaneously. Using multimode timing analysis, all instances of a repeated block can be analyzed and optimized simultaneously. Based on the multimode analysis, instances of a repeated block may be implemented identically or substantially similarly, which can reduce costs associated with implementing the same block more than once (e.g., impact to schedule, CPU/memory resources, ECOs).

摘要翻译： 在各种实施例中，重复块的每个可能的不同实例可以被同时优化用于定时。 重复块的每个实例可以被视为模式，诸如功能模式或测试模式，允许同时执行实现计算。 使用多模时序分析，可以同时分析和优化重复块的所有实例。 基于多模式分析，重复块的实例可以相同地或基本相似地实现，这可以降低与多次实现相同块相关联的成本（例如，对调度，CPU /存储器资源，ECO的影响）。

公开(公告)号：US20070245280A1

公开(公告)日：2007-10-18

申请号：US11734717

申请日：2007-04-12

申请人： Cornells Van Eijk ,  Michail Romesis ,  Roger Carpenter ,  Philippe Sarrazin

发明人： Cornells Van Eijk ,  Michail Romesis ,  Roger Carpenter ,  Philippe Sarrazin

IPC分类号： G06F17/50 ,  G06F9/45

CPC分类号： G06F17/5072

摘要： An electronic design automation method of placing circuit components of an integrated circuit (“IC”) is provided. A synthesized circuit netlist including one or more soft macros is received and a rough global placement of this netlist is performed. A shaper function is determined. The shaper function evaluates a cost of a current placement of the one or more soft macros based on one or more constraints and one or more penalty functions which are associated with the one or more constraints. Moreover, the current placement is optimized to produce a subsequent placement of the one or more soft macros by minimizing the cost. Furthermore, where the netlist includes one or more hard macros, a legalization requirement is applied to the one or more hard macros.

摘要翻译： 提供了一种放置集成电路（“IC”）电路元件的电子设计自动化方法。 接收包括一个或多个软宏的合成电路网表，并且执行该网表的粗略全局放置。 确定成形功能。 成形器功能基于与一个或多个约束相关联的一个或多个约束和一个或多个惩罚函数来评估一个或多个软宏的当前布局的成本。 此外，当前的布局被优化以通过最小化成本来产生一个或多个软宏的后续放置。 此外，网表包括一个或多个硬宏，合法化要求被应用于一个或多个硬宏。

公开(公告)号：US20070245281A1

公开(公告)日：2007-10-18

申请号：US11734757

申请日：2007-04-12

申请人： Michael Riepe ,  Niranjana Balasundaram ,  Menno Verbeek ,  Hong Cai ,  Roger Carpenter ,  Jacob Avidan

发明人： Michael Riepe ,  Niranjana Balasundaram ,  Menno Verbeek ,  Hong Cai ,  Roger Carpenter ,  Jacob Avidan

IPC分类号： G06F17/50 ,  G06F9/45

CPC分类号： G06F17/5072

摘要： A method and system for performing placement-driven physical hierarchy generation in the context of an integrated circuit layout generation system is provided. This generation optimizes the physical hierarchy to improve placement of the cells in the layout, and the associated interconnect routability and delay. A new pre-clustering phase is introduced to maintain as much of the input logical hierarchy as possible while maintaining physical hierarchy quality. And a new cost function is described which is based on measuring the mutual affinity of cells in a virtually-flat placement. The new cost function is used during the new pre-clustering phase, as well as the common clustering, partitioning, and declustering/refinement phases of physical hierarchy generation.

摘要翻译： 提供了一种用于在集成电路布局生成系统的上下文中执行布置驱动物理层次生成的方法和系统。 这一代优化了物理层次结构，以改善布局中单元格的布局，以及相关联的互连可布线性和延迟。 引入了一个新的预聚类阶段，以保持尽可能多的输入逻辑层次结构，同时保持物理层次质量。 并且描述了新的成本函数，其基于测量细胞在几乎平坦的位置中的相互亲和力。 新的成本函数在新的聚类前阶段使用，以及物理层次生成的公共聚类，分割和分解/细化阶段。

公开(公告)号：US20070266359A1

公开(公告)日：2007-11-15

申请号：US11748416

申请日：2007-05-14

申请人： Henrik Esbensen ,  Roger Carpenter ,  Cornelis Van Eijk ,  Kwok-Shing Leung

发明人： Henrik Esbensen ,  Roger Carpenter ,  Cornelis Van Eijk ,  Kwok-Shing Leung

IPC分类号： G06F17/50

CPC分类号： G06F17/5072

摘要： A method for designing integrated circuits includes receiving a floorplan design associated with an integrated circuit. A relative floorplanning constraint is extracted from the floorplan design. The floorplan of the integrated circuit is updated in response to the relative floorplanning constraint. Another method for designing integrated circuits includes receiving a floorplan design associated with an integrated circuit. A set of relative floorplanning constraint is received from the floorplan design. A relative floorplanning constraint is pushed down from the set of relative floorplanning constraints into a partition associated with the floorplan of the integrated circuit. The floorplan is updated in response to the set of relative floorplanning constraints.

摘要翻译： 一种用于设计集成电路的方法包括接收与集成电路相关联的平面图设计。 从平面图设计中提取相对的布局规划约束。 响应于相对布局规划约束更新集成电路的平面图。 设计集成电路的另一种方法包括接收与集成电路相关联的平面图设计。 从平面图设计中接收到一组相对布局规划约束。 相对布局规划约束被从相对布局规划约束集合推下到与集成电路的布局图相关联的分区中。 响应于一组相对布局规划约束更新了平面图。