公开(公告)号：US07246274B2

公开(公告)日：2007-07-17

申请号：US10939028

申请日：2004-09-10

申请人： Jade M. Kizer ,  Christopher J. Madden

发明人： Jade M. Kizer ,  Christopher J. Madden

IPC分类号： G06F11/00

CPC分类号： G06F11/004 ,  G01R31/31709 ,  G01R31/3171 ,  G11C29/022

摘要： An apparatus and method provides prediction of BER for an interface between ICs, such as a processor and a memory device, without using special test equipment. A known data pattern or PRBS is transmitted to a receiver, which compares the received data values with expected data values to determine if a bit error has occurred in an embodiment of the present invention. A center of data eye and the edge of the data eye are sampled (over sampled) in order to determine if a bit error has occurred in an alternate embodiment of the present invention. A first counter is used to count the total number of bits sampled and the second counter is used to count the number of errors that occurred in the total number of bits sampled.

摘要翻译： 一种装置和方法提供了对诸如处理器和存储器装置的IC之间的接口的BER的预测，而不使用特殊的测试设备。 已知的数据模式或PRBS被发送到接收机，接收机将接收到的数据值与期望的数据值进行比较，以确定在本发明的实施例中是否发生了位错误。 数据眼的中心和数据眼的边缘被采样（过采样），以便确定在本发明的替代实施例中是否发生位错误。 第一计数器用于对采样的总位数进行计数，第二计数器用于对所采样总位数中发生的错误数进行计数。

公开(公告)号：US07853837B2

公开(公告)日：2010-12-14

申请号：US11677843

申请日：2007-02-22

申请人： Richard E. Perego ,  Christopher J. Madden

发明人： Richard E. Perego ,  Christopher J. Madden

IPC分类号： G06F11/00 ,  G11C29/00 ,  H04W4/00 ,  H04B17/00

CPC分类号： G06F11/004 ,  G01R31/31709 ,  G01R31/3171 ,  G06F11/00 ,  G11C29/022

摘要： A system, among other embodiments, includes a memory controller having an integrated BER circuit and a plurality of memory devices. The memory controller also includes a control circuit and an interface having at least one transmit circuit to provide write data to at least one of the memory devices and at least one receive circuit to receive read data from at least one of the memory devices. The BER circuit includes a request generator circuit that outputs a request for a memory transaction. A request multiplexer selectively outputs a memory request to the interface from the request generator circuit or the control circuit. A data generator circuit outputs corresponding write data. A first write multiplexer selectively outputs the write data to the interface from the data generator circuit or the control circuit. A read multiplexer selectively receives read data from the receive circuit. The data generator circuit also outputs corresponding write data to a comparator circuit via a second write multiplexer. The comparator circuit outputs an error signal in response to a comparison of the received read data and corresponding stored write data. A counter outputs a count value indicating the number of errors (or bit errors) in response to the error signal. A register interface accesses the count value in the counter and a register that output one or more select signals during a mode of operation. The register interface also allows for controlling the data generator and request generator circuits.

摘要翻译： 除其它实施例之外，系统包括具有集成BER电路和多个存储器件的存储器控​​制器。 存储器控制器还包括控制电路和具有至少一个发射电路的接口，以向至少一个存储器件和至少一个接收电路提供写入数据，以从至少一个存储器件接收读取数据。 BER电路包括输出对存储器事务的请求的请求发生器电路。 请求复用器从请求发生器电路或控制电路选择性地向接口输出存储器请求。 数据发生器电路输出相应的写入数据。 第一写入复用器选择性地将写入数据从数据发生器电路或控制电路输出到接口。 读取多路复用器选择性地从接收电路接收读取数据。 数据发生器电路还经由第二写复用器将对应的写数据输出到比较器电路。 比较器电路响应于所接收的读取数据和对应的存储写入数据的比较而输出错误信号。 计数器响应于误差信号输出指示错误数量（或位错误）的计数值。 寄存器接口访问计数器中的计数值和在操作模式下输出一个或多个选择信号的寄存器。 寄存器接口还允许控制数据发生器和请求发生器电路。