Method of Fabricating Semiconductor Device Having Dual Stress Liner
    1.
    发明申请
    Method of Fabricating Semiconductor Device Having Dual Stress Liner 审中-公开
    制造具有双重应力衬垫的半导体器件的方法

    公开(公告)号:US20080081406A1

    公开(公告)日:2008-04-03

    申请号:US11750491

    申请日:2007-05-18

    IPC分类号: H01L29/739

    摘要: A method of fabricating a semiconductor device comprising providing a substrate including a PMOS region and an NMOS region forming a PMOS gate electrode on the PMOS region and an NMOS gate electrode on the NMOS gate region, respectively, forming a stress liner on the PMOS region formed with the PMOS gate on the PMOS region and the NMOS region formed with the NMOS gate electrode on the NMOS region, and selectively applying radiation onto the stress liner formed on either one of the PMOS region and the NMOS region in an inert vapor ambiance.

    摘要翻译: 一种制造半导体器件的方法,包括在PMOS区上提供包括PMOS区和PMOS栅电极的NMOS区和在NMOS栅区上的NMOS栅电极的衬底,所述衬底在形成的PMOS区上形成应力衬垫 PMOS晶体管上的PMOS栅极和NMOS区域上形成有NMOS栅电极的NMOS区域,并以惰性蒸气气氛,选择性地将辐射施加到形成在PMOS区域和NMOS区域中的任一个上的应力衬垫上。