公开(公告)号：US07595253B2

公开(公告)日：2009-09-29

申请号：US11797827

申请日：2007-05-08

申请人： II-Young Yoon ,  Hong-Jae Shin ,  Nae-In Lee ,  Jae-Ouk Choo ,  Ja-Eung Koo

发明人： II-Young Yoon ,  Hong-Jae Shin ,  Nae-In Lee ,  Jae-Ouk Choo ,  Ja-Eung Koo

IPC分类号： H01L21/76

CPC分类号： H01L21/31053 ,  H01L21/76229

摘要： Example embodiments provide a semiconductor device and a method of forming the same. According to the method, a capping insulation pattern may be formed to cover the top surface of a filling insulation pattern in a trench. The capping insulation pattern may have an etch selectivity according to the filling insulation pattern. As a result, the likelihood that the filling insulation layer may be etched by various cleaning processes and the process removing the buffer insulation pattern may be reduced or prevented.

摘要翻译： 示例性实施例提供半导体器件及其形成方法。 根据该方法，可以形成覆盖绝缘图案以覆盖沟槽中的填充绝缘图案的顶表面。 封盖绝缘图案可以根据填充绝缘图案具有蚀刻选择性。 结果，可以减少或防止填充绝缘层可以通过各种清洁处理蚀刻的可能性以及去除缓冲绝缘图案的过程。

公开(公告)号：US20080081406A1

公开(公告)日：2008-04-03

申请号：US11750491

申请日：2007-05-18

申请人： Jae-ouk Choo ,  II-young Yoon ,  Seo-woo Nam ,  Ja-eung Koo

发明人： Jae-ouk Choo ,  II-young Yoon ,  Seo-woo Nam ,  Ja-eung Koo

IPC分类号： H01L29/739

CPC分类号： H01L21/823425 ,  H01L21/823412 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/7843

摘要： A method of fabricating a semiconductor device comprising providing a substrate including a PMOS region and an NMOS region forming a PMOS gate electrode on the PMOS region and an NMOS gate electrode on the NMOS gate region, respectively, forming a stress liner on the PMOS region formed with the PMOS gate on the PMOS region and the NMOS region formed with the NMOS gate electrode on the NMOS region, and selectively applying radiation onto the stress liner formed on either one of the PMOS region and the NMOS region in an inert vapor ambiance.

摘要翻译： 一种制造半导体器件的方法，包括在PMOS区上提供包括PMOS区和PMOS栅电极的NMOS区和在NMOS栅区上的NMOS栅电极的衬底，所述衬底在形成的PMOS区上形成应力衬垫 PMOS晶体管上的PMOS栅极和NMOS区域上形成有NMOS栅电极的NMOS区域，并以惰性蒸气气氛，选择性地将辐射施加到形成在PMOS区域和NMOS区域中的任一个上的应力衬垫上。