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1.发明申请METHOD FOR ELIMINATING NEGATIVE SLACK IN A NETLIST VIA TRANSFORMATION AND SLACK CATEGORIZATION 有权用于通过变换和滑动分类来消除网络中的负面滑块的方法公开(公告)号：US20090070715A1
公开(公告)日：2009-03-12
申请号：US11853573
申请日：2007-09-11
IPC分类号： G06F17/50
CPC分类号： G06F17/5045 , G06F17/5031 , G06F2217/84
摘要： A method for eliminating negative slack in a netlist representing a chip design uses a contrived timing environment to overlay information onto the design environment during logic and physical synthesis phase. The overlaid timing information determines which netlist transformation provides a maximum leverage for the negative slack elimination and a way for creating a dynamic transformation recipe tuned for each design. The method further provides upper bounds on the negative slack elimination to prevent the netlist transforms from being applied to situations exceeding the capabilities for improving the design.
摘要翻译： 用于消除表示芯片设计的网表中的负松弛的方法使用设计的定时环境来在逻辑和物理合成阶段将信息叠加到设计环境上。 重叠的定时信息确定哪个网表转换为负消除消除提供了最大的杠杆作用，以及为每个设计调整的创建动态变换配方的方法。 该方法进一步提供消极消除的上限，以防止网表变换被应用于超出改进设计能力的情况。
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2.发明授权Method for eliminating negative slack in a netlist via transformation and slack categorization 有权通过转换和松散分类消除网表中的负松弛的方法公开(公告)号：US07810062B2
公开(公告)日：2010-10-05
申请号：US11853573
申请日：2007-09-11
IPC分类号： G06F17/50
CPC分类号： G06F17/5045 , G06F17/5031 , G06F2217/84
摘要： A method for eliminating negative slack in a netlist representing a chip design uses a contrived timing environment to overlay information onto the design environment during logic and physical synthesis phase. The overlaid timing information determines which netlist transformation provides a maximum leverage for the negative slack elimination and a way for creating a dynamic transformation recipe tuned for each design. The method further provides upper bounds on the negative slack elimination to prevent the netlist transforms from being applied to situations exceeding the capabilities for improving the design.
摘要翻译： 用于消除表示芯片设计的网表中的负松弛的方法使用设计的定时环境来在逻辑和物理合成阶段将信息叠加到设计环境上。 重叠的定时信息确定哪个网表转换为负消除消除提供了最大的杠杆作用，以及为每个设计调整的创建动态变换配方的方法。 该方法进一步提供消极消除的上限，以防止网表变换被应用于超出改进设计能力的情况。
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3.发明授权Chip having timing analysis of paths performed within the chip during the design process 有权芯片具有在设计过程中在芯片内执行的路径的定时分析公开(公告)号：US07823108B2
公开(公告)日：2010-10-26
申请号：US11934995
申请日：2007-11-05
申请人： James J. Curtin , Michael J. Cadigan, Jr. , Edward J. Hughes , Kevin M. Mcllvain , Jose L. Neves , Ray Raphy , Douglas S. Search
发明人： James J. Curtin , Michael J. Cadigan, Jr. , Edward J. Hughes , Kevin M. Mcllvain , Jose L. Neves , Ray Raphy , Douglas S. Search
CPC分类号： G06F17/5031
摘要： An integrated circuit chip is made using Genie, a described computer chip design tool which can analyze the data contained within an entire endpoint report, compute relationships between paths based on shared segments, and display this information graphically to the designer. Specifically, Genie groups failing paths into Timing Islands. A timing island is a group of paths which contain at least one shared segment. The most frequently shared segment is sifted to the top of the priority list for each island, and is labeled as the Hub. Thinking of timing islands as a tree, the hub of the island would be the trunk. If you chop the tree down by the trunk, all of the branches, limbs and twigs will fall down too. This is analogous to fixing the timing failures in the hub, and the fix trickling out to each of the segments that dangle off the hub.
摘要翻译： 使用Genie制造的集成电路芯片，Genie是一种描述的计算机芯片设计工具，可以分析整个端点报告中包含的数据，计算基于共享段的路径之间的关系，并将图形显示给设计者。 具体来说，Genie团体失败了进入时代岛的路径。 定时岛是包含至少一个共享段的一组路径。 最常见的共享段被筛选到每个岛的优先级列表的顶部，并被标记为Hub。 将定时岛作为一棵树，岛上的中心将是树干。 如果树干被树干砍下来，所有的树枝，四肢和树枝也会掉下来。 这类似于在集线器中修复定时故障，并且修复程序会逐渐转移到每个从集线器上散落的段。
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4.发明授权Genie: a method for classification and graphical display of negative slack timing test failures 有权Genie：用于分类和图形显示负松弛时序测试故障的方法公开(公告)号：US07356793B2
公开(公告)日：2008-04-08
申请号：US11129784
申请日：2005-05-16
申请人： James J. Curtin , Michael J. Cadigan, Jr. , Edward J. Hughes , Kevin M. McIlvain , Jose L. Neves , Ray Raphy , Douglas S. Search
发明人： James J. Curtin , Michael J. Cadigan, Jr. , Edward J. Hughes , Kevin M. McIlvain , Jose L. Neves , Ray Raphy , Douglas S. Search
IPC分类号： G06F17/50
CPC分类号： G06F17/5031
摘要： Genie is a described computer chip design tool which can analyze the data contained within an entire endpoint report, compute relationships between paths based on shared segments, and display this information graphically to the designer. Specifically, Genie groups failing paths into Timing Islands. A timing island is a group of paths which contain at least one shared segment. The most frequently shared segment is sifted to the top of the priority list for each island, and is labeled as the Hub. Thinking of timing islands as a tree, the hub of the island would be the trunk. If you chop the tree down by the trunk, all of the branches, limbs and twigs will fall down too. This is analogous to fixing the timing failures in the hub, and the fix trickling out to each of the segments that dangle off the hub.
摘要翻译： Genie是一种描述的计算机芯片设计工具，可以分析整个端点报告中包含的数据，计算基于共享段的路径之间的关系，并将图形显示给设计者。 具体来说，Genie团体失败了进入时代岛的路径。 定时岛是包含至少一个共享段的一组路径。 最常见的共享段被筛选到每个岛的优先级列表的顶部，并被标记为Hub。 将定时岛作为一棵树，岛上的中心将是树干。 如果树干被树干砍下来，所有的树枝，四肢和树枝也会掉下来。 这类似于在集线器中修复定时故障，并且修复程序会逐渐转移到每个从集线器上散落的段。
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5.发明授权Methods for placement which maintain optimized behavior, while improving wireability potential 有权保持优化行为，同时提高有线性潜力的放置方法公开(公告)号：US07376924B2
公开(公告)日：2008-05-20
申请号：US11180740
申请日：2005-07-13
IPC分类号： G06F17/50
CPC分类号： G06F17/5031 , G06F17/5072 , G06F2217/84
摘要： A method for determining placement of circuitry during integrated circuit design is presented. The method includes accessing a net list identifying circuitry connections. A plurality of individual net weights are assigned to nets in timing paths within the net list. A composite net weight is determined for said timing paths, the composite net weight being in response to the plurality of individual net weights. Concurrently therewith it is advantageous to utilize our new method of improvements of concurrently proceeding to improve wireability of said design by additional timing optimization and net weight mapping modification steps.
摘要翻译： 提出了一种确定集成电路设计过程中电路布局的方法。 该方法包括访问识别电路连接的网络列表。 在网络列表内的定时路径中将多个单独的净权重分配给网络。 对于所述定时路径确定复合净重，所述复合净重是响应于所述多个个体净重。 与此同时，利用我们的新的同时进行的改进方法是有利的，以通过附加的时序优化和净重映射修改步骤来提高所述设计的可线性。
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6.发明授权System and medium for placement which maintain optimized timing behavior, while improving wireability potential 有权用于放置的系统和介质，其保持优化的定时行为，同时提高可线性潜力公开(公告)号：US07921398B2
公开(公告)日：2011-04-05
申请号：US12047382
申请日：2008-03-13
CPC分类号： G06F17/5031 , G06F17/5072 , G06F2217/84
摘要： A method for determining placement of circuitry during integrated circuit design is presented. The method includes accessing a net list identifying circuitry connections. A plurality of individual net weights are assigned to nets in timing paths within the net list. A composite net weight is determined for said timing paths, the composite net weight being in response to the plurality of individual net weights. Concurrently therewith it is advantageous to utilize our new method of improvements of concurrently proceeding to improve wireability of said design by additional timing optimization and net weight mapping modification steps.
摘要翻译： 提出了一种确定集成电路设计过程中电路布局的方法。 该方法包括访问识别电路连接的网络列表。 在网络列表内的定时路径中将多个单独的净权重分配给网络。 对于所述定时路径确定复合净重，所述复合净重是响应于所述多个个体净重。 与此同时，利用我们的新的同时进行的改进方法是有利的，以通过额外的时序优化和净重映射修改步骤来改善所述设计的可线性。
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7.发明申请System and Medium for Placement Which Maintain Optimized Timing Behavior, While Improving Wireability Potential 有权系统和介质放置，保持优化的时序行为，同时提高可接线性潜力公开(公告)号：US20080163149A1
公开(公告)日：2008-07-03
申请号：US12047382
申请日：2008-03-13
IPC分类号： G06F17/50
CPC分类号： G06F17/5031 , G06F17/5072 , G06F2217/84
摘要： A method for determining placement of circuitry during integrated circuit design is presented. The method includes accessing a net list identifying circuitry connections. A plurality of individual net weights are assigned to nets in timing paths within the net list. A composite net weight is determined for said timing paths, the composite net weight being in response to the plurality of individual net weights. Concurrently therewith it is advantageous to utilize our new method of improvements of concurrently proceeding to improve wireability of said design by additional timing optimization and net weight mapping modification steps.
摘要翻译： 提出了一种确定集成电路设计过程中电路布局的方法。 该方法包括访问识别电路连接的网络列表。 在网络列表内的定时路径中将多个单独的净权重分配给网络。 对于所述定时路径确定复合净重，所述复合净重是响应于所述多个个体净重。 与此同时，利用我们的新的同时进行的改进方法是有利的，以通过附加的时序优化和净重映射修改步骤来提高所述设计的可线性。
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公开(公告)号：US20070300192A1
公开(公告)日：2007-12-27
申请号：US11425721
申请日：2006-06-22
申请人： James J. Curtin , Douglas S. Search
发明人： James J. Curtin , Douglas S. Search
IPC分类号： G06F17/50
CPC分类号： G06F17/5081 , G06F17/5072
摘要： Using a computer and storage, a circuit design process is executed to preserve overall design quality while obtaining quality placements for a full class of pipeline structure signatures. These signatures include classic latch to latch pipelines, as well as a variety of latch to latch and mixed logic pipelines. The process employs a method for optimizing pipeline structure placement in a circuit design, by initiating an analysis of pipeline logic structures for correcting poor quality of result (QOR) placements by identifying poor placements caused by placement algorithmic response to degenerate cases and in the process of analysis preserving high quality placements of global placement and timing to preserve preponderant non-degenerate cases in said circuit design. Then employing a plurality of global placement steps, wherein each subsequent placement's quality of result (QOR) is dependent upon the prior placement's quality of result (QOR), circuits are identified as being involved in a class of degenerate cases, and circuits having poor placements are removed by unplacing them from the global placement solution and also other non-degenerate poor quality placements are corrected.
摘要翻译： 使用计算机和存储器，执行电路设计过程以保持整体设计质量，同时为完整类型的管道结构签名获得高质量的布局。 这些签名包括用于锁存管道的经典锁存器，以及各种锁存器和混合逻辑管线。 该过程采用一种用于优化管道结构放置在电路设计中的方法，通过启动对流水线逻辑结构的分析，通过识别由放置算法对退化情况的响应引起的不良放置，并且在过程中 分析保留了高质量的全局布局和时间安排，以便在所述电路设计中保留主要的非简并案例。 然后采用多个全局放置步骤，其中每个后续放置的结果质量（QOR）取决于先前放置的结果质量（QOR），电路被识别为涉及一类退化情况，并且电路具有差的放置 通过将它们从全局放置解决方案放置而被删除，并且其他非退化劣质布局被更正。
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公开(公告)号：US20090106711A1
公开(公告)日：2009-04-23
申请号：US12348380
申请日：2009-01-05
申请人： James J. Curtin , Douglas S. Search
发明人： James J. Curtin , Douglas S. Search
IPC分类号： G06F17/50
CPC分类号： G06F17/5081 , G06F17/5072
摘要： Using a computer and storage, a circuit design process is executed to preserve overall design quality while obtaining quality placements for a full class of pipeline structure signatures. These signatures include classic latch to latch pipelines, as well as a variety of latch to latch and mixed logic pipelines. The process employs a method for optimizing pipeline structure placement in a circuit design, by initiating an analysis of pipeline logic structures for correcting poor quality of result (QOR) placements by identifying poor placements caused by placement algorithmic response to degenerate cases and in the process of analysis preserving high quality placements of global placement and timing to preserve preponderant non-degenerate cases in said circuit design. Then employing a plurality of global placement steps, wherein each subsequent placement's quality of result (QOR) is dependent upon the prior placement's quality of result (QOR), circuits are identified as being involved in a class of degenerate cases, and circuits having poor placements are removed by unplacing them from the global placement solution and also other non-degenerate poor quality placements are corrected.
摘要翻译： 使用计算机和存储器，执行电路设计过程以保持整体设计质量，同时为完整类型的管道结构签名获得高质量的布局。 这些签名包括用于锁存管道的经典锁存器，以及各种锁存器和混合逻辑管线。 该过程采用一种用于优化管道结构放置在电路设计中的方法，通过启动对流水线逻辑结构的分析，通过识别由放置算法对退化情况的响应引起的不良放置，并且在过程中 分析保留了高质量的全局布局和时间安排，以便在所述电路设计中保留主要的非简并案例。 然后采用多个全局放置步骤，其中每个后续放置的结果质量（QOR）取决于先前放置的结果质量（QOR），电路被识别为涉及一类退化情况，并且电路具有差的放置 通过将它们从全局放置解决方案放置而被删除，并且其他非退化劣质布局被更正。
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公开(公告)号：US07496866B2
公开(公告)日：2009-02-24
申请号：US11425721
申请日：2006-06-22
申请人： James J. Curtin , Douglas S. Search
发明人： James J. Curtin , Douglas S. Search
IPC分类号： G06F17/50
CPC分类号： G06F17/5081 , G06F17/5072
摘要： Using a computer and storage, a circuit design process is executed to preserve overall design quality while obtaining quality placements for a full class of pipeline structure signatures. These signatures include classic latch to latch pipelines, as well as a variety of latch to latch and mixed logic pipelines. The process employs a method for optimizing pipeline structure placement in a circuit design, by initiating an analysis of pipeline logic structures for correcting poor quality of result (QOR) placements by identifying poor placements caused by placement algorithmic response to degenerate cases and in the process of analysis preserving high quality placements of global placement and timing to preserve preponderant non-degenerate cases in said circuit design. Then employing a plurality of global placement steps, wherein each subsequent placement's quality of result (QOR) is dependent upon the prior placement's quality of result (QOR), circuits are identified as being involved in a class of degenerate cases, and circuits having poor placements are removed by unplacing them from the global placement solution and also other non-degenerate poor quality placements are corrected.
摘要翻译： 使用计算机和存储器，执行电路设计过程以保持整体设计质量，同时为完整类型的管道结构签名获得高质量的布局。 这些签名包括用于锁存管道的经典锁存器，以及各种锁存器和混合逻辑管线。 该过程采用一种用于优化管道结构放置在电路设计中的方法，通过启动对流水线逻辑结构的分析，通过识别由放置算法对退化情况的响应引起的不良放置，并且在过程中 分析保留了高质量的全局布局和时间安排，以便在所述电路设计中保留主要的非简并案例。 然后采用多个全局放置步骤，其中每个后续放置的结果质量（QOR）取决于先前放置的结果质量（QOR），电路被识别为涉及一类退化情况，并且电路具有差的放置 通过将它们从全局放置解决方案放置而被删除，并且其他非退化劣质布局被更正。
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