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    Dynamic cache coherency snooper presence with variable snoop latency
    1.
    发明授权
    Dynamic cache coherency snooper presence with variable snoop latency 有权
    动态缓存一致性snooper存在与可变侦听延迟

    公开(公告)号：US06985972B2

    公开(公告)日：2006-01-10

    申请号：US10264163

    申请日：2002-10-03

    申请人： James Norris Dieffenderfer ,  Bernard Charles Drerup ,  Jaya Prakash Subramaniam Ganasan ,  Richard Gerard Hofmann ,  Thomas Andrew Sartorius ,  Thomas Philip Speier ,  Barry Joe Wolford

    发明人： James Norris Dieffenderfer ,  Bernard Charles Drerup ,  Jaya Prakash Subramaniam Ganasan ,  Richard Gerard Hofmann ,  Thomas Andrew Sartorius ,  Thomas Philip Speier ,  Barry Joe Wolford

    IPC分类号： G06F13/28 ,  G06F12/00

    CPC分类号： G06F13/366 ,  G06F12/0831 ,  G06F2212/1028 ,  G06F2213/0038 ,  Y02D10/13 ,  Y02D10/14

    摘要： A data processing system with a snooper that is capable of dynamically enabling and disabling its snooping capabilities (i.e., snoop detect and response). The snooper is connected to a bus controller via a plurality of interconnects, including a snooperPresent signal, a snoop response signal and a snoop detect signal. When the snooperPresent signal is asserted, subsequent snoop requests are sent to the snooper, and the snooper is polled for a snoop response. Each snooper is capable of responding at different times (i.e., each snooper operates with different snoop latencies). The bus controller individually tracks the snoop response received from each snooper with the snooperPresent signal enabled. Whenever the snooper wishes to deactivate its snooping capabilities/operations, the snooper de-asserts the snooperPresent signal. The bus controller recognizes this as an indication that the snooper is unavailable. Thus, when the bus controller broadcasts subsequent snoop requests, the bus controller does not send the snoop request to the snooper.

    摘要翻译： 具有能够动态地启用和禁用其窥探能力（即，窥探检测和响应）的窥探者的数据处理系统。 窥探者通过多个互连连接到总线控制器，包括窥探信号，窥探响应信号和窥探检测信号。 当snooperPresent信号被断言时，后续的窥探请求被发送到snooper，并且窥探者被轮询以进行侦听响应。 每个窥探者都能够在不同的时间进行响应（即，每个窥探者使用不同的侦听延迟进行操作）。 总线控制器单独跟踪snooperPresent信号启用时从每个窥探者接收的窥探响应。 只要窥探者希望取消其窥探能力/操作，窥探者将断言snooperPresent信号。 总线控制器将此识别为snooper不可用的指示。 因此，当总线控制器广播后续的窥探请求时，总线控制器不向窥探者发送窥探请求。

    Ensuring orderly forward progress in granting snoop castout requests
    3.
    发明授权
    Ensuring orderly forward progress in granting snoop castout requests 失效
    确保在发出侦听请求时有序地推进进度

    公开(公告)号：US07127562B2

    公开(公告)日：2006-10-24

    申请号：US10458998

    申请日：2003-06-11

    申请人： James Norris Dieffenderfer ,  Bernard Charles Drerup ,  Jaya Prakash Ganasan ,  Richard Gerard Hofmann ,  Thomas Andrew Sartorius ,  Thomas Philip Speier ,  Barry Joe Wolford

    发明人： James Norris Dieffenderfer ,  Bernard Charles Drerup ,  Jaya Prakash Ganasan ,  Richard Gerard Hofmann ,  Thomas Andrew Sartorius ,  Thomas Philip Speier ,  Barry Joe Wolford

    IPC分类号： G06F12/00

    CPC分类号： G06F12/0831

    摘要： A method and system for ensuring orderly forward progress in granting snoop castout requests. Masters may include a tag (“request tag”) in their transfer requests to a bus macro. The request tag indicates the order of the request issued by the master. If the bus macro determines that the transfer request is snoopable, then the bus macro broadcasts a snoop request that includes the request tag. If a snoop controller determines that the address in the snoop request is a hit to a modified coherency granule in an associated cache, then the master associated with that snoop controller transmits a castout request to the bus macro that includes the request tag associated with the snoop request. The bus macro uses the request tag to determine whether the castout request is a response to the oldest in a series of pipelined snoop requests to be serviced.

    摘要翻译： 一种方法和系统，用于确保在发出侦听请求时有序地前进进度。 主机可以在其传送请求中包括一个标签（“请求标签”）到总线宏。 请求标签指示主机发出的请求的顺序。 如果总线宏确定传输请求是可窥探的，则总线宏广播包含请求标签的窥探请求。 如果窥探控制器确定窥探请求中的地址是对相关高速缓存中修改的相关性粒度的命中，则与该监听控制器相关联的主机向总线宏发送包含与窥探相关联的请求标签的总线宏的抛出请求 请求。 总线宏使用请求标签来确定castout请求是否是对一系列待管理的流水线侦听请求中的最早的响应。

    Minimizing memory barriers when enforcing strongly-ordered requests in a weakly-ordered processing system
    5.
    发明授权
    Minimizing memory barriers when enforcing strongly-ordered requests in a weakly-ordered processing system 有权
    在弱有序处理系统中强制强制排序的请求时，最大限度地减少内存障碍

    公开(公告)号：US07500045B2

    公开(公告)日：2009-03-03

    申请号：US11254939

    申请日：2005-10-20

    申请人： Richard Gerard Hofmann ,  James Norris Dieffenderfer ,  Thomas Sartorius ,  Thomas Philip Speier ,  Jaya Prakash Subramaniam Ganasan

    发明人： Richard Gerard Hofmann ,  James Norris Dieffenderfer ,  Thomas Sartorius ,  Thomas Philip Speier ,  Jaya Prakash Subramaniam Ganasan

    IPC分类号： G06F13/36 ,  G06F12/00

    CPC分类号： G06F13/1621

    摘要： The disclosure is directed to a weakly-ordered processing system and method for enforcing strongly-ordered memory access requests in a weakly-ordered processing system. The processing system includes a plurality of memory devices and a plurality of processors. A bus interconnect is configured to interface the processors to the memory devices. The bus interconnect is further configured to enforce an ordering constraint for a strongly-ordered memory access request from an originating processor to a target memory device by sending a memory barrier to each of the other memory devices accessible by the originating processor, except for those memory devices that the bus interconnect can confirm have no unexecuted memory access requests from the originating processor.

    摘要翻译： 本公开涉及一种用于在弱有序处理系统中强制执行强有序存储器访问请求的弱有序处理系统和方法。 处理系统包括多个存储器件和多个处理器。 总线互连被配置为将处理器连接到存储器设备。 总线互连还被配置为通过向由始发处理器可访问的其他存储器设备中的每一个发送存储器障碍来强制执行来自始发处理器到目标存储器设备的强有序存储器访问请求的排序约束，除了那些存储器 总线互连可以确认的设备没有来自始发处理器的未执行的存储器访问请求。

    Apparatus and methods to reduce castouts in a multi-level cache hierarchy
    8.
    发明授权
    Apparatus and methods to reduce castouts in a multi-level cache hierarchy 有权
    减少多级缓存层次结构中的丢弃的装置和方法

    公开(公告)号：US08078803B2

    公开(公告)日：2011-12-13

    申请号：US11669245

    申请日：2007-01-31

    申请人： Thomas Philip Speier ,  James Norris Dieffenderfer ,  Thomas Andrew Sartorius

    发明人： Thomas Philip Speier ,  James Norris Dieffenderfer ,  Thomas Andrew Sartorius

    IPC分类号： G06F12/00

    CPC分类号： G06F12/0897 ,  G06F12/0804 ,  G06F12/128 ,  G06F2212/1028 ,  Y02D10/13

    摘要： Techniques and methods are used to control allocations to a higher level cache of cache lines displaced from a lower level cache. The allocations of the displaced cache lines are prevented for displaced cache lines that are determined to be redundant in the next level cache, whereby castouts are controlled. To such ends, a line is selected to be displaced in a lower level cache. Information associated with the selected line is identified which indicates that the selected line is present in a higher level cache. An allocation of the selected line in the higher level cache is prevented based on the identified information.

    摘要翻译： 技术和方法用于控制从较低级别缓存中移位的高速缓存行的更高级缓存的分配。 对于被确定为在下一级高速缓存中是冗余的移位高速缓存线，防止移位的高速缓存行的分配，从而控制转储。 为此，选择在下一级缓存中移位的行。 识别与所选行相关联的信息，其指示所选择的行存在于较高级别的高速缓存中。 基于所识别的信息来防止在较高级别高速缓存中的所选行的分配。

    Auto-Ordering of Strongly Ordered, Device, and Exclusive Transactions Across Multiple Memory Regions
    9.
    发明申请
    Auto-Ordering of Strongly Ordered, Device, and Exclusive Transactions Across Multiple Memory Regions 有权
    在多个内存区域自动排序强顺序，设备和独占交易

    公开(公告)号：US20130151799A1

    公开(公告)日：2013-06-13

    申请号：US13315370

    申请日：2011-12-09

    申请人： Jason Lawrence Panavich ,  James Norris Dieffenderfer ,  Thomas Andrew Sartorius ,  Thomas Philip Speier

    发明人： Jason Lawrence Panavich ,  James Norris Dieffenderfer ,  Thomas Andrew Sartorius ,  Thomas Philip Speier

    IPC分类号： G06F12/00

    CPC分类号： G06F13/1621

    摘要： Efficient techniques are described for controlling ordered accesses in a weakly ordered storage system. A stream of memory requests is split into two or more streams of memory requests and a memory access counter is incremented for each memory request. A memory request requiring ordered memory accesses is identified in one of the two or more streams of memory requests. The memory request requiring ordered memory accesses is stalled upon determining a previous memory request from a different stream of memory requests is pending. The memory access counter is decremented for each memory request guaranteed to complete. A count value in the memory access counter that is different from an initialized state of the memory access counter indicates there are pending memory requests. The memory request requiring ordered memory accesses is processed upon determining there are no further pending memory requests.

    摘要翻译： 描述了用于控制弱订单存储系统中有序访问的高效技术。 存储器请求流被分成两个或更多个存储器请求流，并且每个存储器请求增加存储器访问计数器。 需要有序存储器访问的存储器请求在两个或更多个存储器请求流中的一个中被识别。 在从不同的存储器请求流确定先前的存储器请求正在等待时，需要有序存储器访问的存储器请求被停止。 对于保证完成的每个存储器请求，存储器访问计数器递减。 与存储器访问计数器的初始化状态不同的存储器访问计数器中的计数值指示存在未决存储器请求。 在确定没有进一步的未决存储器请求时，处理需要有序存储器访问的存储器请求。

    Apparatus and Methods to Reduce Castouts in a Multi-Level Cache Hierarchy
    10.
    发明申请
    Apparatus and Methods to Reduce Castouts in a Multi-Level Cache Hierarchy 有权
    在多级缓存层次结构中减少铸件的装置和方法

    公开(公告)号：US20120059995A1

    公开(公告)日：2012-03-08

    申请号：US13292651

    申请日：2011-11-09

    申请人： Thomas Philip Speier ,  James Norris Dieffenderfer ,  Thomas Andrew Sartorius

    发明人： Thomas Philip Speier ,  James Norris Dieffenderfer ,  Thomas Andrew Sartorius

    IPC分类号： G06F12/08

    CPC分类号： G06F12/0897 ,  G06F12/0804 ,  G06F12/128 ,  G06F2212/1028 ,  Y02D10/13

    摘要： Techniques and methods are used to reduce allocations to a higher level cache of cache lines displaced from a lower level cache. The allocations of the displaced cache lines are prevented for displaced cache lines that are determined to be redundant in the next level cache, whereby castouts are reduced. To such ends, a line is selected to be displaced in a lower level cache. Information associated with the selected line is identified which indicates that the selected line is present in a higher level cache. An allocation of the selected line in the higher level cache is prevented based on the identified information. Preventing an allocation of the selected line saves power that would be associated with the allocation.

    摘要翻译： 技术和方法用于减少从较低级别缓存中移位的高速缓存行的更高级缓存的分配。 对于在下一级高速缓存中被确定为冗余的移位高速缓存线，防止移位的高速缓存行的分配，从而减少了突发。 为此，选择在下一级缓存中移位的行。 识别与所选行相关联的信息，其指示所选择的行存在于较高级别的高速缓存中。 基于所识别的信息来防止在较高级别高速缓存中的所选行的分配。 防止所选线路的分配节省与分配相关联的功率。