-
公开(公告)号：US11637638B2
公开(公告)日：2023-04-25
申请号：US17543915
申请日：2021-12-07
摘要： A method at a receiver comprises receiving a signal conveying symbols at respective positions within a clock cycle, the symbols comprising a data set consisting of data symbols and a pilot set consisting of pilot symbols; determining detected phases of the symbols based on the signal; generating first phase estimates based on the detected phases of a subset of the pilot set, and reference phases of the subset of the pilot set, the first phase estimates being associated with the positions of the pilot set; and generating second phase estimates based on the detected phases of the pilot set, reference phases of the pilot set, and the first phase estimates, the second phase estimates being associated with the positions of the pilot set and of at least a subset of the data set; and applying rotations to the detected phases of the symbols based on the second phase estimates.
-
公开(公告)号：US20080222594A1
公开(公告)日：2008-09-11
申请号：US11716187
申请日：2007-03-09
申请人： Eric Maniloff , Ronald Gagnon , Blake Toplis
发明人： Eric Maniloff , Ronald Gagnon , Blake Toplis
IPC分类号： H03K17/693
CPC分类号： H03K19/1731 , H03K19/17744 , H04L25/14
摘要： Each data lane connected to a FPGA and forming part of a SFI channel may be trained independently to enable the outputs from the FPGA to be aligned. In operation, a known fixed pattern is repeated on each of the data lanes with the exception of the data lane being trained. The short fixed pattern is smaller than an SERDES capture range so that the SERDES may temporarily lock onto the short fixed pattern for all data lanes other than the lane being trained. Training data is then transmitted on the lane being trained and the preskew delay for that lane is adjusted until the receiving component indicates that the lanes are aligned. This process may iterate to find acceptable preskew delay values for all lanes. By training the lanes one at a time and using a short repeating pattern on the untrained lanes, the SERDES may register that the untrained lanes are operating correctly so that the feedback from the SERDES is related only to the lane being trained.
摘要翻译： 可以独立地训练连接到FPGA并形成SFI通道的一部分的每个数据通道，以使来自FPGA的输出能够对准。 在操作中，除了正在训练的数据通道之外，在每个数据通道上重复已知的固定模式。 短的固定模式小于SERDES捕获范围，以便SERDES可能暂时锁定到除被训练的通道之外的所有数据通道的短固定模式。 然后训练数据在被训练的车道上传送，并且调整该车道的预定时延，直到接收组件指示车道对齐。 该过程可以迭代以找到所有车道的可接受的前置时间延迟值。 通过一次训练车道并在未经训练的车道上使用短暂的重复模式，SERDES可以注册未经训练的车道正常运行，以便来自SERDES的反馈仅与被训练的车道相关。
-
公开(公告)号：US20050228900A1
公开(公告)日：2005-10-13
申请号：US10821090
申请日：2004-04-08
申请人： David Stuart , Markus Wandel , Blake Toplis
发明人： David Stuart , Markus Wandel , Blake Toplis
IPC分类号： G06F15/16 , G06F15/173 , H04L12/56
CPC分类号： H04L47/10 , G06Q40/025 , H04L47/30 , H04L47/39
摘要： An apparatus and a method for sender-initiated credit recovery in a closed-loop credit based flow control system, includes assigning a number of credits to a sender unit in the credit based flow control system. The method also includes decrementing a credit count in the sender unit in response to the sender sending data to the receiver and incrementing the credit count in the sender unit in response to receiving returned credits from the receiver unit. The method also includes determining if a loss or gain in the number of credits in the credit based flow control system has occurred and adjusting the credit count based on the determined loss or gain.
摘要翻译： 一种在基于闭环信用的流量控制系统中用于发送者发起的信用恢复的装置和方法，包括：将信用数量分配给基于信用的流量控制系统中的发送者单元。 该方法还包括响应于发送者向接收者发送数据并递增发送者单元中的信用计数，响应于接收来自接收器单元的返回信用，递减发送方单元中的信用计数。 该方法还包括确定是否发生了基于信用的流量控制系统中的信用数量的损失或增益，并且基于所确定的损失或增益来调整信用计数。
-
公开(公告)号：US07480730B2
公开(公告)日：2009-01-20
申请号：US10821090
申请日：2004-04-08
申请人： David Stuart , Markus Wandel , Blake Toplis
发明人： David Stuart , Markus Wandel , Blake Toplis
IPC分类号： G06F15/16 , H04L5/22 , G06F15/173
CPC分类号： H04L47/10 , G06Q40/025 , H04L47/30 , H04L47/39
摘要： An apparatus and a method for sender-initiated credit recovery in a closed-loop credit based flow control system, includes assigning a number of credits to a sender unit in the credit based flow control system. The method also includes decrementing a credit count in the sender unit in response to the sender sending data to the receiver and incrementing the credit count in the sender unit in response to receiving returned credits from the receiver unit. The method also includes determining if a loss or gain in the number of credits in the credit based flow control system has occurred and adjusting the credit count based on the determined loss or gain.
摘要翻译： 一种在基于闭环信用的流量控制系统中用于发送者发起的信用恢复的装置和方法，包括：将信用数量分配给基于信用的流量控制系统中的发送者单元。 该方法还包括响应于发送者向接收者发送数据并递增发送者单元中的信用计数，响应于接收来自接收器单元的返回信用，递减发送方单元中的信用计数。 该方法还包括确定是否发生了基于信用的流量控制系统中的信用数量的损失或增益，并且基于所确定的损失或增益来调整信用计数。
-
公开(公告)号：US07467056B2
公开(公告)日：2008-12-16
申请号：US11716187
申请日：2007-03-09
申请人： Eric Maniloff , Ronald Gagnon , Blake Toplis
发明人： Eric Maniloff , Ronald Gagnon , Blake Toplis
IPC分类号： H04B13/00
CPC分类号： H03K19/1731 , H03K19/17744 , H04L25/14
摘要： Each data lane connected to a FPGA and forming part of a SFI channel may be trained independently to enable the outputs from the FPGA to be aligned. In operation, a known fixed pattern is repeated on each of the data lanes with the exception of the data lane being trained. The short fixed pattern is smaller than an SERDES capture range so that the SERDES may temporarily lock onto the short fixed pattern for all data lanes other than the lane being trained. Training data is then transmitted on the lane being trained and the preskew delay for that lane is adjusted until the receiving component indicates that the lanes are aligned. This process may iterate to find acceptable preskew delay values for all lanes. By training the lanes one at a time and using a short repeating pattern on the untrained lanes, the SERDES may register that the untrained lanes are operating correctly so that the feedback from the SERDES is related only to the lane being trained.
-
-
-
-
搜索结果
5 条记录 (耗时 0.02 秒)
