公开(公告)号：US06631385B2

公开(公告)日：2003-10-07

申请号：US09497136

申请日：2000-02-03

申请人： Jang Sun Lee ,  June Kim ,  Hun Soon Lee ,  Myung Joon Kim ,  Gil Rok Oh ,  Jae Soo Yoo ,  Seok Il Song

发明人： Jang Sun Lee ,  June Kim ,  Hun Soon Lee ,  Myung Joon Kim ,  Gil Rok Oh ,  Jae Soo Yoo ,  Seok Il Song

IPC分类号： G06F1730

CPC分类号： G06F11/1474 ,  Y10S707/99933 ,  Y10S707/99953

摘要： A recovery method for a high-dimensional index structure is disclosed, in which a reinsert operation is employed based on ARIES (algorithm for recovery and isolation exploiting semantics) and a page-oriented redo and a logical undo. Further, a recording medium on which a program for carrying out the above method is recorded is disclosed, the program being readable by a computer. The recovery method for a high-dimensional index structure employing a reinsert operation according to the present invention includes the following steps. At a first step, an entry is inserted into a node, a minimum bounding region is adjusted, an overflow is processed, and a log record is stored. At a second step, the log record thus stored is recovered.

摘要翻译： 公开了一种高维度索引结构的恢复方法，其中基于ARIES（用于恢复和隔离开发语义的算法）和面向页面的重做和逻辑撤销来采用重新插入操作。 此外，公开了记录有用于执行上述方法的程序的记录介质，该程序可由计算机读取。 根据本发明的采用重新插入操作的高维索引结构的恢复方法包括以下步骤。 在第一步，将条目插入节点，调整最小边界区域，处理溢出，并存储日志记录。 在第二步，恢复如此存储的日志记录。

公开(公告)号：US06415361B1

公开(公告)日：2002-07-02

申请号：US09487348

申请日：2000-01-19

申请人： Sang Man Moh ,  Jong Seok Han ,  An Do Ki ,  Woo Jong Hahn ,  Suk Han Yoon ,  Gil Rok Oh

发明人： Sang Man Moh ,  Jong Seok Han ,  An Do Ki ,  Woo Jong Hahn ,  Suk Han Yoon ,  Gil Rok Oh

IPC分类号： G06F1200

CPC分类号： G06F12/0828 ,  G06F2212/2542

摘要： An apparatus for controlling a cache in a computing node, which is located between a node bus and an interconnection network to perform a cache coherence protocol, includes: a node bus interface for interfacing with the node bus; an interconnection network interface for interfacing with the interconnection network; a cache control logic means for controlling the cache to perform the cache coherence protocol; bus-side dual-port transaction buffers coupled between said node bus interface and said cache control logic means for buffering transaction requested and replied from or to local processors contained in the computing node; and network-side dual-port transaction buffers coupled between said interconnection network interface and said cache control logic for buffering transaction requested and replied from or to remote processors contained in another computing node coupled to the interconnection network.

摘要翻译： 一种用于控制位于节点总线和互连网络之间以执行高速缓存一致性协议的计算节点中的高速缓存的装置包括：用于与节点总线接口的节点总线接口; 用于与互连网络对接的互连网络接口; 用于控制高速缓存以执行高速缓存一致性协议的高速缓存控制逻辑装置; 耦合在所述节点总线接口和所述高速缓存控制逻辑装置之间的总线端双端口事务缓冲器，用于缓冲从计算节点中包含的本地处理器请求和应答的事务; 以及耦合在所述互连网络接口和所述高速缓存控制逻辑之间的网络侧双端口事务缓冲器，用于缓存从耦合到互连网络的另一个计算节点中包含的远程处理器请求和回复的事务。