公开(公告)号：US06415361B1

公开(公告)日：2002-07-02

申请号：US09487348

申请日：2000-01-19

申请人： Sang Man Moh ,  Jong Seok Han ,  An Do Ki ,  Woo Jong Hahn ,  Suk Han Yoon ,  Gil Rok Oh

发明人： Sang Man Moh ,  Jong Seok Han ,  An Do Ki ,  Woo Jong Hahn ,  Suk Han Yoon ,  Gil Rok Oh

IPC分类号： G06F1200

CPC分类号： G06F12/0828 ,  G06F2212/2542

摘要： An apparatus for controlling a cache in a computing node, which is located between a node bus and an interconnection network to perform a cache coherence protocol, includes: a node bus interface for interfacing with the node bus; an interconnection network interface for interfacing with the interconnection network; a cache control logic means for controlling the cache to perform the cache coherence protocol; bus-side dual-port transaction buffers coupled between said node bus interface and said cache control logic means for buffering transaction requested and replied from or to local processors contained in the computing node; and network-side dual-port transaction buffers coupled between said interconnection network interface and said cache control logic for buffering transaction requested and replied from or to remote processors contained in another computing node coupled to the interconnection network.

摘要翻译： 一种用于控制位于节点总线和互连网络之间以执行高速缓存一致性协议的计算节点中的高速缓存的装置包括：用于与节点总线接口的节点总线接口; 用于与互连网络对接的互连网络接口; 用于控制高速缓存以执行高速缓存一致性协议的高速缓存控制逻辑装置; 耦合在所述节点总线接口和所述高速缓存控制逻辑装置之间的总线端双端口事务缓冲器，用于缓冲从计算节点中包含的本地处理器请求和应答的事务; 以及耦合在所述互连网络接口和所述高速缓存控制逻辑之间的网络侧双端口事务缓冲器，用于缓存从耦合到互连网络的另一个计算节点中包含的远程处理器请求和回复的事务。

公开(公告)号：US6055599A

公开(公告)日：2000-04-25

申请号：US143787

申请日：1998-08-31

申请人： Jong-Seok Han ,  Kyoung Park ,  Won-Sae Sim ,  Woo-Jong Hahn ,  Kee-Wook Rim

发明人： Jong-Seok Han ,  Kyoung Park ,  Won-Sae Sim ,  Woo-Jong Hahn ,  Kee-Wook Rim

IPC分类号： G06F15/173 ,  G06F13/00

CPC分类号： G06F15/17393

摘要： The present invention relates to a hierarchical crossbar inter-connection network for a cluster-based parallel processing computer. A crossbar network is composed of the "n" number of crossbar switches which is byte sliced, eight links for connecting eight nodes, and two links for connecting other clusters. In addition, one low-level cluster is formed by connecting a maximum of eight processing nodes between the two crossbar networks, and one high-level cluster is formed with a maximum of eight low-level clusters and the four crossbar networks. Moreover, one next high-level clusters formed with a maximum of eight high-level clusters and the eight crossbar networks for scalability.

摘要翻译： 本发明涉及一种用于基于群集的并行处理计算机的层级交叉连接网络。 交叉网络由“n”个字节切换的交叉开关组成，用于连接八个节点的八个链路和用于连接其他集群的两个链路组成。 此外，通过在两个交叉网络之间连接最多八个处理节点来形成一个低级集群，并且一个高级集群形成有最多八个低级集群和四个交叉网络。 此外，一个下一个高级别集群最多可组成八个高级集群，八个交叉网络可扩展。

公开(公告)号：US5751934A

公开(公告)日：1998-05-12

申请号：US747685

申请日：1996-11-12

申请人： Jong-Seok Han ,  Woo-Jong Hahn ,  Suk-Han Yoon

发明人： Jong-Seok Han ,  Woo-Jong Hahn ,  Suk-Han Yoon

IPC分类号： G06F15/16 ,  G06F15/173 ,  H04Q3/68 ,  G06F13/00 ,  H04Q11/04

CPC分类号： H04Q3/685 ,  G06F15/17393

摘要： A non-blocking fault tolerant gamma network for a multi-processor system is disclosed, including: N dual links respectively connected to n source nodes, and for transmitting data input; a first stage made up with n 2.times.3 switching devices for outputting data transmitted from the N dual links; a second stage made up with n 3.times.4 switching devices for outputting data output from the first stage; a third stage to n-1 stage made up with (n-2).times.N 4.times.4 switching devices for receiving data output from the second stage at the third stage and outputting the data to n-1 stage; an n stage made up with n 4.times.2 circuits for receiving data output from the n-1 stage and outputting the data; and n dual links connected to n destination nodes for transmitting data output from the n stage, whereby the links, which connect the n source nodes, switching devices of the interconnection network and n destination nodes, are designed according to the connection formula of the certain regulation, thus simultaneously set all paths between a plurality of sources and a plurality of destinations, and tolerate a single-switching fault or a single-link fault in the interconnection network.

摘要翻译： 公开了一种用于多处理器系统的非阻塞容错伽马网络，包括：分别连接到n个源节点的N个双链路，以及用于发送数据输入; 由n个2x3切换装置构成的第一阶段，用于输出从N个双重链路传送的数据; 由用于输出从第一级输出的数据的n×3×4切换装置构成的第二级; 由（n-2）×N×4×4个开关装置构成的第n-1级的第3级，用于接收从第3级的第2级输出的数据，并将数据输出到n-1级; 由n 4x2电路构成的n级，用于接收从n-1级输出的数据并输出数据; 以及连接到n个目的地节点的n个双链路，用于发送从n个阶段输出的数据，其中连接n个源节点的链路，互连网络的交换设备和n个目的地节点根据特定的连接公式来设计 从而同时设置多个源和多个目的地之间的所有路径，并且容许互连网络中的单交换故障或单链路故障。

公开(公告)号：US06871237B2

公开(公告)日：2005-03-22

申请号：US10418127

申请日：2003-04-18

申请人： Jong Seok Han ,  Yong Seok Choi ,  Sang Man Moh ,  Myung-Joon Kim ,  Kee-Wook Rim

发明人： Jong Seok Han ,  Yong Seok Choi ,  Sang Man Moh ,  Myung-Joon Kim ,  Kee-Wook Rim

IPC分类号： G06F13/00 ,  G06F13/14 ,  G06F13/28

CPC分类号： G06F13/28

摘要： The present invention is a data transfer protocol control system with a host bus interface that includes a transmitting/receiving command DMA, a transmitting data DMA and a receiving data DMA for controlling data transfer protocol with a host bus interface considering characteristic, usage frequency, simultaneous processing functions of the command DMA and the data DMAs. A host interface bus is efficiently used and bus usage ratio is distributed properly to support transfer flow properly and improve the entire system performance. The data transfer protocol control system with a host bus interface includes a transmitting/receiving command DMA for instructing the command DMA request buffer to read and write command message data, a transmitting data DMA for instructing the transmitting data DMA request buffer to read the command message data, a receiving data DMA for instructing the receiving data DMA request buffer to write the command message data and a data transfer protocol control device for putting read information, write information and message data on a host bus, receiving message data and a transfer response signal and delivering the message data through the response buffer of the corresponding DMA.

摘要翻译： 本发明是一种具有主机总线接口的数据传输协议控制系统，其包括发送/接收命令DMA，发送数据DMA和用于通过主机总线接口控制数据传输协议的接收数据DMA，考虑特性，使用频率，同时 命令DMA和数据DMA的处理功能。 主机接口总线被有效地使用，总线使用率正确分配，以适当地支持传输流程，并提高整个系统性能。 具有主机总线接口的数据传输协议控制系统包括用于指令DMA请求缓冲器读取和写入命令消息数据的发送/接收命令DMA，用于指示发送数据DMA请求缓冲器读取命令消息的发送数据DMA 数据，用于指示接收数据DMA请求缓冲器写入命令消息数据的接收数据DMA和用于将读信息，写信息和消息数据放在主机总线上的数据传输协议控制装置，接收消息数据和传送响应信号 并通过相应DMA的响应缓冲区传送消息数据。

公开(公告)号：US06505289B1

公开(公告)日：2003-01-07

申请号：US09475049

申请日：1999-12-30

申请人： Jong Seok Han ,  Sang Man Moh ,  Woo Jong Hahn ,  Suk Han Yoon

发明人： Jong Seok Han ,  Sang Man Moh ,  Woo Jong Hahn ,  Suk Han Yoon

IPC分类号： G06F1300

CPC分类号： G06F15/17337

摘要： The present invention relates to a node connection apparatus. The 3-link node interconnection apparatus and parallel processing apparatus using the same confirm expanding nodes freely, only using fixed three connecting links, and are suitable to normal packaging method because of easy dividing into 2n (n>1) nodes. The apparatuses comprise the following nodes. The first node has three links connected to other nodes respectively. The second node has three links, one links of them is connected to the first node, and the other two links are in charge of connection of X+ direction, X− direction. The third node has three links, one link of them is connected to the first node, and the other two links are in charge of connection of Y+ direction, Y− direction. The fourth node has three links, one link of them is connected to the first node, and the other two links are in charge of connection of Z+ direction, Z− direction.

摘要翻译： 节点连接装置技术领域本发明涉及节点连接装置。 3链节点互连设备和使用该链路节点的并行处理设备可以自由地确定扩展节点，只使用固定的三个连接链路，由于容易划分成2n（n> 1）个节点，因此适合正常的封装方法。 这些装置包括以下节点。 第一个节点分别连接到其他节点的三个链路。 第二节点有三个链路，一个链路连接到第一个节点，另外两个链路负责连接X +方向，X方向。 第三节点有三个链路，一个链路连接到第一个节点，另外两个链路负责Y +方向，Y方向的连接。 第四个节点有三个链路，一个链路连接到第一个节点，另外两个链路负责Z +方向，Z方向的连接。