公开(公告)号：US09245910B2

公开(公告)日：2016-01-26

申请号：US14547650

申请日：2014-11-19

Applicant: Japan Display Inc.

Inventor： Yasunori Fukumoto ,  Toshihide Jinnai ,  Koji Sato

IPC: H01L21/77 ,  H01L27/12 ,  G02F1/1333 ,  G02F1/1343 ,  H01L29/768

CPC classification number: H01L27/1259 ,  G02F1/133345 ,  G02F1/134363 ,  H01L29/768

Abstract: According to one embodiment, provided is an array substrate that can effectively prevent an oxide conductive film and a silicon nitride film on the oxide conductive film from peeling without deteriorating reliability. A method for manufacturing the array substrate includes a surface treatment step and a nitride film forming step. In the surface treatment step, by plasma discharge, the oxide conductive film is cleaned without being reduced, and surface layers of the insulating film layer not covered by the oxide conductive film and portions of the insulating film layer in the regions covered by the oxide conductive film are etched to form recesses leading to portions under the oxide conductive film. In the nitride film forming step, successively from the surface treatment step, the silicon nitride film is formed by plasma CVD so as to cover the recesses and the oxide conductive film.

Abstract translation: 根据一个实施方式，提供了能够有效地防止氧化物导电膜上的氧化物导电膜和氮化硅膜剥离而不劣化可靠性的阵列基板。 阵列基板的制造方法包括表面处理工序和氮化膜形成工序。 在表面处理步骤中，通过等离子体放电，氧化物导电膜被清洁而不被还原，并且绝缘膜层的表面层未被氧化物导电膜覆盖，并且绝缘膜层的部分被氧化物导电覆盖的区域 蚀刻以形成通向氧化物导电膜下方的部分的凹部。 在氮化膜形成工序中，从表面处理工序开始，通过等离子体CVD形成氮化硅膜，以覆盖凹部和氧化物导电膜。