公开(公告)号：US11846860B2

公开(公告)日：2023-12-19

申请号：US18164809

申请日：2023-02-06

Applicant: Japan Display Inc.

Inventor： Akihiro Hanada ,  Toshihide Jinnai ,  Isao Suzumura ,  Hajime Watakabe ,  Ryo Onodera

IPC: G02F1/1362 ,  G02F1/1368 ,  H01L29/786 ,  H10K50/86 ,  H10K59/131

CPC classification number: G02F1/1368 ,  G02F1/136209 ,  G02F1/136277 ,  G02F1/136286 ,  H01L29/78633 ,  H01L29/78672 ,  H10K50/865 ,  H10K59/131

Abstract: A display device including: a substrate; a first thin film transistor of polysilicon semiconductor, a second thin film transistor of oxide semiconductor; a first light shading film opposing to the polysilicon semiconductor, and a second light shading film opposing to the oxide semiconductor; a first insulating film, a second insulating film which is constituted from plural insulating films, and a third insulating film superposed in this order; a first through hole penetrating the second insulating film and not penetrating the first insulating film and the third insulating film; a second through hole penetrating the first insulating film and the third insulating film; the first light shading film connects with a first conductive component, a part of the first conductive component exists on the third insulating film, through the second through hole.

公开(公告)号：US09245910B2

公开(公告)日：2016-01-26

申请号：US14547650

申请日：2014-11-19

Applicant: Japan Display Inc.

Inventor： Yasunori Fukumoto ,  Toshihide Jinnai ,  Koji Sato

IPC: H01L21/77 ,  H01L27/12 ,  G02F1/1333 ,  G02F1/1343 ,  H01L29/768

CPC classification number: H01L27/1259 ,  G02F1/133345 ,  G02F1/134363 ,  H01L29/768

Abstract: According to one embodiment, provided is an array substrate that can effectively prevent an oxide conductive film and a silicon nitride film on the oxide conductive film from peeling without deteriorating reliability. A method for manufacturing the array substrate includes a surface treatment step and a nitride film forming step. In the surface treatment step, by plasma discharge, the oxide conductive film is cleaned without being reduced, and surface layers of the insulating film layer not covered by the oxide conductive film and portions of the insulating film layer in the regions covered by the oxide conductive film are etched to form recesses leading to portions under the oxide conductive film. In the nitride film forming step, successively from the surface treatment step, the silicon nitride film is formed by plasma CVD so as to cover the recesses and the oxide conductive film.

Abstract translation: 根据一个实施方式，提供了能够有效地防止氧化物导电膜上的氧化物导电膜和氮化硅膜剥离而不劣化可靠性的阵列基板。 阵列基板的制造方法包括表面处理工序和氮化膜形成工序。 在表面处理步骤中，通过等离子体放电，氧化物导电膜被清洁而不被还原，并且绝缘膜层的表面层未被氧化物导电膜覆盖，并且绝缘膜层的部分被氧化物导电覆盖的区域 蚀刻以形成通向氧化物导电膜下方的部分的凹部。 在氮化膜形成工序中，从表面处理工序开始，通过等离子体CVD形成氮化硅膜，以覆盖凹部和氧化物导电膜。

公开(公告)号：US20150140794A1

公开(公告)日：2015-05-21

申请号：US14540458

申请日：2014-11-13

Applicant: Japan Display Inc.

Inventor： Naoya ITO ,  Toshihide Jinnai ,  Hirofumi Mizukoshi

IPC: H01L21/02

CPC classification number: H01L21/02238 ,  H01L21/02052 ,  H01L21/02323 ,  H01L21/02343 ,  H01L21/02422 ,  H01L21/02532 ,  H01L21/02667 ,  H01L21/02686 ,  H01L21/02691 ,  H01L27/1274

Abstract: According to one embodiment, provided is a polycrystallization method for polycrystallizing an amorphous semiconductor film that has a natural oxide film on the surface . The polycrystallization method includes a step of cleaning the natural oxide film while leaving the natural oxide film on the surface of the amorphous semiconductor film, and a step of polycrystallizing the amorphous semiconductor film in the state where the natural oxide film is left.

Abstract translation: 根据一个实施方案，提供了一种用于在表面上具有自然氧化物膜的非晶半导体膜多晶化的多晶化方法。 多晶化方法包括在将天然氧化物膜留在非晶半导体膜的表面上的同时清洁天然氧化物膜的步骤，以及在留下自然氧化物膜的状态下使非晶半导体膜多晶化的步骤。

公开(公告)号：US11824063B2

公开(公告)日：2023-11-21

申请号：US17148653

申请日：2021-01-14

Applicant: Japan Display Inc.

Inventor： Akihiro Hanada ,  Toshihide Jinnai

IPC: H01L27/12 ,  H01L29/66 ,  H01L29/786

CPC classification number: H01L27/1229 ,  H01L27/1225 ,  H01L29/66969 ,  H01L29/7869

Abstract: An object of the present invention is to provide a technology using which, in a thin film transistor using oxide semiconductor, the resistance of a channel region of the oxide semiconductor is made high, and at the same time the resistances of a source region and a drain region of the oxide semiconductor are made low. There is provided a semiconductor device including: a thin film transistor including oxide semiconductor, the oxide semiconductor including a channel region, a drain region, and a source region; a gate insulating film formed on the channel region; an aluminum oxide film formed on the gate insulating film; and a gate electrode formed on the aluminum oxide film, wherein the aluminum oxide film has a region that covers neither the drain region nor the source region in a plane view.

公开(公告)号：US11550195B2

公开(公告)日：2023-01-10

申请号：US17506694

申请日：2021-10-21

Applicant: Japan Display Inc.

Inventor： Toshihide Jinnai ,  Hajime Watakabe ,  Akihiro Hanada ,  Ryo Onodera ,  Isao Suzumura

IPC: G02F1/1362 ,  G02F1/1368 ,  H01L29/786 ,  H01L27/12 ,  H01L27/32

Abstract: A display device including a substrate having a first TFT of an oxide semiconductor and a second TFT of a polysilicon semiconductor comprising: the oxide semiconductor 109 is covered by a first insulating film, a first drain electrode 110 is connected to the oxide semiconductor 109 via a first through hole 132 formed in the first insulating film, a first source electrode 111 is connected to the oxide semiconductor 109 via second through hole 133 formed in the first insulating film in the first TFT, a second insulating film is formed covering the first drain electrode 110 and the first source electrode 111, a drain wiring connects 12 to the first drain electrode 110 via a third through hole 130 formed in the second insulating film, a source wiring 122 is connected to the first source electrode 111 via a fourth through hole 131 formed in the second insulating film.

公开(公告)号：US11362113B2

公开(公告)日：2022-06-14

申请号：US16986462

申请日：2020-08-06

Applicant: Japan Display Inc.

Inventor： Hajime Watakabe ,  Toshihide Jinnai ,  Ryo Onodera ,  Akihiro Hanada

IPC: H01L27/00 ,  H01L29/00 ,  H01L27/12 ,  H01L29/66 ,  H01L29/786

Abstract: There is provided a technique that enables a reduction in the display failure of a display device and the improvement of the yields of the display device in a display device that adopts a semiconductor device including a thin film transistor using an oxide semiconductor. A semiconductor device according to an embodiment includes a thin film transistor having an oxide semiconductor. The oxide semiconductor has a drain region, a source region, and a channel region provided between the drain region and the source region. The thin film transistor includes a gate insulating film provided on the channel region, an aluminum oxide film provided on the gate insulating film, an insulating film provided on the aluminum oxide film, and a gate electrode provided on the insulating film.

公开(公告)号：US09384965B2

公开(公告)日：2016-07-05

申请号：US14540458

申请日：2014-11-13

Applicant: Japan Display Inc.

Inventor： Naoya Ito ,  Toshihide Jinnai ,  Hirofumi Mizukoshi

IPC: H01L21/20 ,  H01L21/02 ,  H01L27/12

CPC classification number: H01L21/02238 ,  H01L21/02052 ,  H01L21/02323 ,  H01L21/02343 ,  H01L21/02422 ,  H01L21/02532 ,  H01L21/02667 ,  H01L21/02686 ,  H01L21/02691 ,  H01L27/1274

Abstract: According to one embodiment, provided is a polycrystallization method for polycrystallizing an amorphous semiconductor film that has a natural oxide film on the surface. The polycrystallization method includes a step of cleaning the natural oxide film while leaving the natural oxide film on the surface of the amorphous semiconductor film, and a step of polycrystallizing the amorphous semiconductor film in the state where the natural oxide film is left.

Abstract translation: 根据一个实施方案，提供了一种用于在表面上具有自然氧化物膜的非晶半导体膜多晶化的多晶化方法。 多晶化方法包括在将天然氧化物膜留在非晶半导体膜的表面上的同时清洁天然氧化物膜的步骤，以及在留下自然氧化物膜的状态下使非晶半导体膜多晶化的步骤。

公开(公告)号：US12072595B2

公开(公告)日：2024-08-27

申请号：US18503351

申请日：2023-11-07

Applicant: Japan Display Inc.

Inventor： Akihiro Hanada ,  Toshihide Jinnai ,  Isao Suzumura ,  Hajime Watakabe ,  Ryo Onodera

IPC: G02F1/1368 ,  G02F1/1362 ,  H01L29/786 ,  H10K50/86 ,  H10K59/131

CPC classification number: G02F1/1368 ,  G02F1/136209 ,  G02F1/136277 ,  G02F1/136286 ,  H01L29/78633 ,  H01L29/78672 ,  H10K50/865 ,  H10K59/131

Abstract: A display device including: a substrate; a first thin film transistor of polysilicon semiconductor, a second thin film transistor of oxide semiconductor; a first light shading film opposing to the polysilicon semiconductor, and a second light shading film opposing to the oxide semiconductor; a first insulating film, a second insulating film which is constituted from plural insulating films, and a third insulating film superposed in this order; a first through hole penetrating the second insulating film and not penetrating the first insulating film and the third insulating film; a second through hole penetrating the first insulating film and the third insulating film; the first light shading film connects with a first conductive component, a part of the first conductive component exists on the third insulating film, through the second through hole.

公开(公告)号：US11721765B2

公开(公告)日：2023-08-08

申请号：US17499908

申请日：2021-10-13

Applicant: Japan Display Inc.

Inventor： Hajime Watakabe ,  Tomoyuki Ito ,  Toshihide Jinnai ,  Isao Suzumura ,  Akihiro Hanada ,  Ryo Onodera

IPC: H01L21/00 ,  H01L29/786 ,  H01L27/12 ,  H01L29/24 ,  H01L29/423 ,  H01L29/49 ,  H01L21/02 ,  H01L21/426 ,  H01L21/4757 ,  H01L21/4763 ,  H01L29/66 ,  G02F1/1368

CPC classification number: H01L29/78627 ,  H01L21/02178 ,  H01L21/02565 ,  H01L21/426 ,  H01L21/47573 ,  H01L21/47635 ,  H01L27/124 ,  H01L27/127 ,  H01L27/1225 ,  H01L27/1251 ,  H01L29/24 ,  H01L29/42384 ,  H01L29/4908 ,  H01L29/66969 ,  H01L29/7869 ,  H01L29/78633 ,  H01L29/78675 ,  G02F1/1368 ,  H01L2029/42388

Abstract: A semiconductor device includes thin film transistors each having an oxide semiconductor. The oxide semiconductor has a channel region, a drain region, a source region, and low concentration regions which are lower in impurity concentration than the drain region and the source region. The low concentration regions are located between the channel region and the drain region, and between the channel region and the source region. Each of the thin film transistors has a gate insulating film on the channel region and the low concentration regions, an aluminum oxide film on a first part of the gate insulating film, the first part being located on the channel region, and a gate electrode on the aluminum oxide film and a second part of the gate insulating film, the second part being located on the low concentration regions.

公开(公告)号：US11630361B2

公开(公告)日：2023-04-18

申请号：US17471881

申请日：2021-09-10

Applicant: Japan Display Inc.

Inventor： Akihiro Hanada ,  Toshihide Jinnai ,  Isao Suzumura ,  Hajime Watakabe ,  Ryo Onodera

IPC: G02F1/1368 ,  G02F1/1362 ,  H01L29/786

Abstract: A display device including: a substrate; a first thin film transistor of polysilicon semiconductor, a second thin film transistor of oxide semiconductor; a first light shading film opposing to the polysilicon semiconductor, and a second light shading film opposing to the oxide semiconductor; a first insulating film, a second insulating film which is constituted from plural insulating films, and a third insulating film superposed in this order; a first through hole penetrating the second insulating film and not penetrating the first insulating film and the third insulating film; a second through hole penetrating the first insulating film and the third insulating film; the first light shading film connects with a first conductive component, a part of the first conductive component exists on the third insulating film, through the second through hole.