摘要:
An apparatus is provided for using multiple thread contexts to improve processing performance of a single thread. When an exceptional instruction is encountered, the exceptional instruction and any predicted instructions are reloaded into a buffer of a first thread context. A state of the register file at the time of encountering the exceptional instruction is maintained in a register file of the first thread context. The instructions in the pipeline are executed speculatively using a second register file in a second thread context. During speculative execution, cache misses may cause loading of data to the cache may be performed. Results of the speculative execution are written to the second register file. When a stopping condition is met, contents of the first register file are copied to the second register file and the reloaded instructions are released to the execution pipeline.
摘要:
For each predicted branch within a processor, an entry is maintained within a branch history table. The entry within the branch history table also includes an indication of the past record for that particular branch instruction, which indicates how correct the branch prediction has been in the past. When the field value associated with the predicted branch exceeds a certain threshold, indicating that the past predictions associated with that branch instruction have been at an unacceptable level, then the speculative branch instructions dispatching is suspended for that particular branch instruction. Alternative embodiments utilize a global indicator for suspending or cancelling instruction dispatch when the frequency of previous incorrect branch predictions increases beyond a preselected threshold.
摘要:
A method, system and processor for improving the performance of an in-order processor. A processor may include an execution unit with an execution pipeline that includes a backup pipeline and a regular pipeline. The backup pipeline may store a copy of the instructions issued to the regular pipeline. The execution pipeline may include logic for allowing instructions to flow from the backup pipeline to the regular pipeline following the flushing of the instructions younger than the exception detected in the regular pipeline. By maintaining a backup copy of the instructions issued to the regular pipeline, instructions may not need to be flushed from separate execution pipelines and re-fetched. As a result, one may complete the results of the execution units to the architected state out of order thereby allowing the completion point to vary among the different execution pipelines.
摘要:
A method, system and processor for improving the performance of an in-order processor. A processor may include an execution unit with an execution pipeline that includes a backup pipeline and a regular pipeline. The backup pipeline may store a copy of the instructions issued to the regular pipeline. The execution pipeline may include logic for allowing instructions to flow from the backup pipeline to the regular pipeline following the flushing of the instructions younger than the exception detected in the regular pipeline. By maintaining a backup copy of the instructions issued to the regular pipeline, instructions may not need to be flushed from separate execution pipelines and re-fetched. As a result, one may complete the results of the execution units to the architected state out of order thereby allowing the completion point to vary among the different execution pipelines.
摘要:
A method, system and processor for improving the performance of an in-order processor. A processor may include an execution unit with an execution pipeline that includes a backup pipeline and a regular pipeline. The backup pipeline may store a copy of the instructions issued to the regular pipeline. The execution pipeline may include logic for allowing instructions to flow from the backup pipeline to the regular pipeline following the flushing of the instructions younger than the exception detected in the regular pipeline. By maintaining a backup copy of the instructions issued to the regular pipeline, instructions may not need to be flushed from separate execution pipelines and re-fetched. As a result, one may complete the results of the execution units to the architected state out of order thereby allowing the completion point to vary among the different execution pipelines.