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1.发明申请Computer program product for design verification using sequential and combinational transformations 有权用于使用顺序和组合变换进行设计验证的计算机程序产品公开(公告)号：US20080178132A1
公开(公告)日：2008-07-24
申请号：US12055692
申请日：2008-03-26
IPC分类号： G06F17/50
CPC分类号： G06F17/504
摘要： System and software for verifying that a model of an integrated circuit satisfies its specification includes performing a sequence of at least one sequential transformation on a sequential model of the integrated circuit to produce a simplified sequential model of the integrated circuit. Thereafter, the simplified sequential model is unfolded for N time steps to create a combinational representation of the design. A sequence of at least one combinational transformation algorithms is then performed on the unfolded design to produce a simplified unfolded model. Finally, an exhaustive search algorithm is performed on the simplified unfolded model. The sequence of sequential transformations may include a sequential redundancy removal (SRR) algorithm and/or another sequential algorithm such as a retiming transformation. The combinational transformations may include a combinational redundancy removal algorithm or a logic re-encoding algorithm. The exhaustive search includes performing an exhaustive satisfiability search by propagating a binary decision diagram (BDD) through the netlist.
摘要翻译： 用于验证集成电路的模型满足其规范的系统和软件包括在集成电路的顺序模型上执行至少一个顺序变换的序列以产生集成电路的简化的顺序模型。 此后，简化的顺序模型展开N个时间步骤以创建设计的组合表示。 然后在展开的设计上执行至少一个组合变换算法的序列以产生简化的展开模型。 最后，对简化的展开模型进行详尽的搜索算法。 顺序变换的顺序可以包括顺序冗余删除（SRR）算法和/或诸如重定时变换的其他顺序算法。 组合变换可以包括组合冗余删除算法或逻辑重新编码算法。 详尽的搜索包括通过网表传播二进制决策图（BDD）来执行穷尽的可满足性搜索。
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2.发明授权Computer program product for design verification using sequential and combinational transformations 有权用于使用顺序和组合变换进行设计验证的计算机程序产品公开(公告)号：US07996800B2
公开(公告)日：2011-08-09
申请号：US12055692
申请日：2008-03-26
IPC分类号： G06F17/50
CPC分类号： G06F17/504
摘要： System and software for verifying that a model of an integrated circuit satisfies its specification includes performing a sequence of at least one sequential transformation on a sequential model of the integrated circuit to produce a simplified sequential model of the integrated circuit. Thereafter, the simplified sequential model is unfolded for N time steps to create a combinational representation of the design. A sequence of at least one combinational transformation algorithms is then performed on the unfolded design to produce a simplified unfolded model. Finally, an exhaustive search algorithm is performed on the simplified unfolded model. The sequence of sequential transformations may include a sequential redundancy removal (SRR) algorithm and/or another sequential algorithm such as a retiming transformation. The combinational transformations may include a combinational redundancy removal algorithm or a logic re-encoding algorithm. The exhaustive search includes performing an exhaustive satisfiability search by propagating a binary decision diagram (BDD) through the netlist.
摘要翻译： 用于验证集成电路的模型满足其规范的系统和软件包括在集成电路的顺序模型上执行至少一个顺序变换的序列以产生集成电路的简化的顺序模型。 此后，简化的顺序模型展开N个时间步骤以创建设计的组合表示。 然后在展开的设计上执行至少一个组合变换算法的序列以产生简化的展开模型。 最后，对简化的展开模型进行详尽的搜索算法。 顺序变换的顺序可以包括顺序冗余删除（SRR）算法和/或诸如重定时变换的其他顺序算法。 组合变换可以包括组合冗余删除算法或逻辑重新编码算法。 详尽的搜索包括通过网表传播二进制决策图（BDD）来执行穷尽的可满足性搜索。
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公开(公告)号：US07360185B2
公开(公告)日：2008-04-15
申请号：US11050606
申请日：2005-02-03
IPC分类号： G06F17/50
CPC分类号： G06F17/504
摘要： System and software for verifying that a model of an integrated circuit satisfies its specification includes performing a sequence of at least one sequential transformation on a sequential model of the integrated circuit to produce a simplified sequential model of the integrated circuit. Thereafter, the simplified sequential model is unfolded for N time steps to create a combinational representation of the design. A sequence of at least one combinational transformation algorithms is then performed on the unfolded design to produce a simplified unfolded model. Finally, an exhaustive search algorithm is performed on the simplified unfolded model. The sequence of sequential transformations may include a sequential redundancy removal (SRR) algorithm and/or another sequential algorithm such as a retiming transformation. The combinational transformations may include a combinational redundancy removal algorithm or a logic re-encoding algorithm. The exhaustive search includes performing an exhaustive satisfiability search by propagating a binary decision diagram (BDD) through the netlist.
摘要翻译： 用于验证集成电路的模型满足其规范的系统和软件包括在集成电路的顺序模型上执行至少一个顺序变换的序列以产生集成电路的简化的顺序模型。 此后，简化的顺序模型展开N个时间步骤以创建设计的组合表示。 然后在展开的设计上执行至少一个组合变换算法的序列以产生简化的展开模型。 最后，对简化的展开模型进行详尽的搜索算法。 顺序变换的顺序可以包括顺序冗余删除（SRR）算法和/或诸如重定时变换的其他顺序算法。 组合变换可以包括组合冗余删除算法或逻辑重新编码算法。 详尽的搜索包括通过网表传播二进制决策图（BDD）来执行穷尽的可满足性搜索。
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