公开(公告)号：US06522271B2

公开(公告)日：2003-02-18

申请号：US10096161

申请日：2002-03-12

申请人： Jean Louis Calvignac ,  Jeffrey James Lynch ,  Daniel James Sucher ,  Fabrice Jean Verplanken

发明人： Jean Louis Calvignac ,  Jeffrey James Lynch ,  Daniel James Sucher ,  Fabrice Jean Verplanken

IPC分类号： H03M700

CPC分类号： H03M7/20

摘要： A 2-bit communication channel is made to transmit complex data patterns by partitioning a digital string into 3-bit binary patterns which are encoded into 4 bits binary pattern and transmitted over the 2-bit communication channel in pairs using adjacent clock cycles on the 2-bit channel. Pre-defined ones of the 4-bit encoded data structures are used for framing on the channel and cannot be used to transmit data.

公开(公告)号：US5875308A

公开(公告)日：1999-02-23

申请号：US878025

申请日：1997-06-18

申请人： Patrick Kevin Egan ,  Daniel Frank Moertl ,  Thomas James Osten ,  Daniel James Sucher

发明人： Patrick Kevin Egan ,  Daniel Frank Moertl ,  Thomas James Osten ,  Daniel James Sucher

IPC分类号： G06F13/40 ,  G06F13/00

CPC分类号： G06F13/4081

摘要： An enhanced peripheral component interconnect (PCI) architecture for a data-processing system is described. In accordance with the method and system of the present invention, a peripheral component interconnect (PCI) architecture for a data-processing system comprises a PCI host bus, a number of PCI local buses, and a PCI hot-plug bridge. Each of the local PCI buses has an adapter card slot. The PCI hot-plug bridge, connected between the PCI host bus and the PCI local buses, is utilized for controlling power to each of the PCI local buses, such that a PCI adapter card may be removed from or added to any one of the adapter card slots during power up while there is processing ongoing within adapter card(s) situated in other adapter card slot(s).

摘要翻译： 描述了用于数据处理系统的增强的外围组件互连（PCI）架构。 根据本发明的方法和系统，用于数据处理系统的外围部件互连（PCI）架构包括PCI主机总线，多个PCI本地总线和PCI热插拔桥。 每个本地PCI总线都有一个适配卡插槽。 连接在PCI主机总线和PCI本地总线之间的PCI热插拔桥被用于控制每个PCI本地总线的电源，使得PCI适配器卡可以从适配器中移除或添加到任何一个适配器 在位于其他适配卡插槽中的适配器卡内进行处理时，在通电期间卡插槽。

公开(公告)号：US07310345B2

公开(公告)日：2007-12-18

申请号：US10002085

申请日：2001-11-01

申请人： William John Goetzinger ,  Glen Howard Handlogten ,  James Francis Mikos ,  David Alan Norgaard ,  Daniel James Sucher

发明人： William John Goetzinger ,  Glen Howard Handlogten ,  James Francis Mikos ,  David Alan Norgaard ,  Daniel James Sucher

IPC分类号： H04L12/54

CPC分类号： H04L49/901 ,  H04L47/50 ,  H04L47/623

摘要： A scheduler for a network processor includes one or more scheduling queues. Each scheduling queue defines a respective sequence in which flows are to be serviced. A respective empty indicator is associated with each scheduling queue to indicate whether the respective scheduling queue is empty. By referring to the empty indicators, it is possible to avoid wasting operating cycles of the scheduler on searching scheduling queues that are empty.

摘要翻译： 网络处理器的调度器包括一个或多个调度队列。 每个调度队列定义要在其中服务流的相应序列。 相应的空指示符与每个调度队列相关联，以指示相应的调度队列是否为空。 通过参考空指示符，可以避免在搜索空的调度队列时浪费调度器的操作周期。