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    Vector address conflict resolution with vector population count functionality
    2.
    发明授权
    Vector address conflict resolution with vector population count functionality 有权
    矢量地址冲突解决与矢量人口计数功能

    公开(公告)号：US09411592B2

    公开(公告)日：2016-08-09

    申请号：US13731005

    申请日：2012-12-29

    Applicant: INTEL CORPORATION

    Inventor： Robert Valentine ,  Mark J. Charney ,  Jesus Corbal ,  Milind B. Girkar ,  Christopher J. Hughes ,  Elmoustapha Ould-Ahmed-Vall ,  Brett L. Toll

    IPC: G06F9/30 ,  G06F9/38 ,  G06F7/60 ,  H03M7/20

    CPC classification number: G06F9/30145 ,  G06F7/607 ,  G06F9/30014 ,  G06F9/30018 ,  G06F9/30032 ,  G06F9/30036 ,  G06F9/3836 ,  G06F9/3887 ,  H03M7/20

    Abstract: Instructions and logic provide SIMD address conflict resolution with vector population count functionality. Some embodiments include processors with a register with a variable plurality of data fields, each of the data fields to store a variable second plurality of bits. A destination register has corresponding data fields, each of these data fields to store a count of the number of bits set to one for corresponding data fields. Responsive to decoding a vector population count instruction, execution units count the number of bits set to one for each of data fields in the register, and store the counts in corresponding data fields of the first destination register. Vector population count instructions can be used with variable sized elements and conflict masks to generate iteration counts and completion masks to be used each iteration to resolve dependencies in gather-modify-scatter SIMD operations.

    Abstract translation: 指令和逻辑提供SIMD地址冲突解决与向量群体计数功能。 一些实施例包括具有可变多个数据字段的寄存器的处理器，每个数据字段用于存储可变的第二多个位。 目的地寄存器具有对应的数据字段，这些数据字段中的每一个用于存储为相应的数据字段设置为1的位数的计数。 响应于对向量群体计数指令进行解码，执行单元对寄存器中的每个数据字段设置为1的位数进行计数，并将计数存储在第一目的地寄存器的相应数据字段中。 矢量人口计数指令可用于可变大小的元素和冲突掩码，以生成迭代计数和完成掩码，以便在每次迭代中使用以解决聚集修改散射SIMD操作中的依赖关系。

    MTR and RLL code design and encoder and decoder
    3.
    发明授权
    MTR and RLL code design and encoder and decoder 有权
    MTR和RLL码设计及编码器及解码器

    公开(公告)号：US09071266B2

    公开(公告)日：2015-06-30

    申请号：US14151656

    申请日：2014-01-09

    Applicant: SK hynix memory solutions inc.

    Inventor： Zheng Wu ,  Jason Bellorado ,  Marcus Marrow

    IPC: H03M5/00 ,  H03M7/00 ,  H03M5/14 ,  H03M7/20

    CPC classification number: H03M5/145 ,  H03M7/20 ,  H03M7/46

    Abstract: An array f(n) is received for n=1, . . . , N where N is a length of a codeword. An array g(n) is received for n=1, . . . , N where N is a length of a codeword. Input data is encoded to satisfy an MTR constraint and a RLL constraint using the array f(n) and the array g(n).

    Abstract translation: 对于n = 1，接收数组f（n）。 。 。 ，N，其中N是码字的长度。 对于n = 1，接收数组g（n）。 。 。 ，N，其中N是码字的长度。 使用阵列f（n）和阵列g（n）对输入数据进行编码以满足MTR约束和RLL约束。

    Method and apparatus for transmitting and receiving data using a self clocking link protocol
    5.
    发明授权
    Method and apparatus for transmitting and receiving data using a self clocking link protocol 有权
    使用自定时链路协议发送和接收数据的方法和装置

    公开(公告)号：US06763477B1

    公开(公告)日：2004-07-13

    申请号：US09629494

    申请日：2000-07-31

    Applicant: James McGee

    Inventor： James McGee

    IPC: G06F104

    CPC classification number: H03M7/20

    Abstract: A receiver receives data using a restricted transition 2-out-of-4 encoding protocol that prohibits a transition from one encoding back to the same encoding, thereby ensuring that at least two signals change every transition. One encoding is assigned a meaning of “repeat”, thereby ensuring that it is possible to transmit the same value repeatedly, and another encoding is assigned a meaning of “invert”, thereby ensuring that is possible to transmit complement values repeatedly. The receiver driver includes a link differential receiver, a link receiver detector, a link receiver clock recovery unit, a link receiver valid data extender, and a link receiver decoder. A pair of signals carrying data encoded with the protocol are provided to the link differential receiver, which in turn asserts exactly one of six encoding signals that are provided to the link receiver detector. Using the six encoding signals, the link receiver detector generates 30 detector signals, which are provided to the link receiver clock recovery unit and the link receiver valid data extender. The clock recovery unit recovers a clock signal from the transitions and the link receiver valid data extender extends the period in which the data is valid. Finally, the link receiver decoder extracts the data carried by the protocol and provides the data to other circuits of the receiving block.

    Abstract translation: 接收机使用禁止从一个编码转换到相同编码的限制转换2/4的编码协议接收数据，从而确保至少两个信号在每次转换时都改变。 一个编码被赋予“重复”的含义，从而确保可以重复发送相同的值，并且另一个编码被赋予“反转”的含义，从而确保可以重复传输补码。 接收机驱动器包括链路差分接收机，链路接收机检测器，链路接收机时钟恢复单元，链路接收机有效数据扩展器和链路接收机解码器。 携带用协议编码的数据的一对信号被提供给链路差分接收机，链路差分接收机进一步断言提供给链路接收机检测器的六个编码信号中的一个。 使用六个编码信号，链路接收机检测器产生30个检测器信号，其被提供给链路接收机时钟恢复单元和链路接收机有效数据扩展器。 时钟恢复单元从转换恢复时钟信号，并且链路接收器有效数据延长器延长数据有效的周期。 最后，链路接收机解码器提取协议携带的数据，并将数据提供给接收块的其他电路。

    Decoding circuit, code conversion circuit and method
    6.
    发明申请
    Decoding circuit, code conversion circuit and method 有权
    解码电路，代码转换电路和方法

    公开(公告)号：US20020158782A1

    公开(公告)日：2002-10-31

    申请号：US10121702

    申请日：2002-04-15

    Applicant: NEC CORPORATION

    Inventor： Miki Takahashi ,  Hiraku Takahashi

    IPC: H03M007/20

    CPC classification number: H03M7/20

    Abstract: To provide a code conversion circuit and a code converting method which are effective in reducing the circuit size. A 2N-bit signal, composed of a N-bit signal and a signal obtained on inverting respective N-bits of said N-bit signal, where N is an integer not less than 2, is received as an input, one of the 2N-bits is inverted to output 2N types decoded signals, in which one bit or plural neighboring (Nnull1) bits of the 2N-bits are of a first value, with the remaining bits being of a second value.

    Abstract translation: 提供有效减少电路尺寸的代码转换电路和代码转换方法。 接收N比特信号和将N为不小于2的整数的N位信号的各N位反相得到的信号作为输入，2N 位反转以输出2N类型的解码信号，其中2N位的一位或多个相邻（N-1）位是第一值，其余位是第二值。

    Asynchronous data conversion circuit
    7.
    发明授权
    Asynchronous data conversion circuit 失效
    异步数据转换电路

    公开(公告)号：US06301264B1

    公开(公告)日：2001-10-09

    申请号：US09089006

    申请日：1998-06-02

    Applicant: Jeffrey J. Holm

    Inventor： Jeffrey J. Holm

    IPC: H03M720

    CPC classification number: G06F13/4018 ,  H03M7/20

    Abstract: A data conversion circuit and method are disclosed for converting an N-bit data stream to an M-bit data stream. A FIFO memory device having multiple N-bit memory locations receives as an input consecutive N-bit sets of data and stores each consecutively received N-bit set of data in consecutive memory locations. A write pointer identifies a next available memory location at which the next N-bit set of data is to be stored. A first read pointer identifies a first memory location containing a first portion of a first M-bit set of data. A second read pointer identifies a second memory location containing a last portion of the first M-bit set of data. Provided as the first M-bit set of data are each of the N-bit memory locations between and including the memory location identified by the first read pointer and the memory location identified by the second read pointer.

    Abstract translation: 公开了一种用于将N位数据流转换为M位数据流的数据转换电路和方法。 具有多个N位存储器位置的FIFO存储器件接收作为输入的连续的N位数据组，并将连续接收的N位数据组存储在连续的存储单元中。 写指针标识下一个可用存储器位置，在该存储器位置将存储下一个N位数据集。 第一读指针标识包含第一M位数据集的第一部分的第一存储器位置。 第二读指针标识包含第一M位数据集的最后部分的第二存储器位置。 当第一M位数据组是由第一读指针识别的存储器位置和由第二读指针标识的存储器位置之间的N位存储器位置中的每一个时提供。

    Compact glitchless M of N decoder circuit for digital to analog converters
    9.
    发明授权
    Compact glitchless M of N decoder circuit for digital to analog converters 失效
    用于数模转换器的N个解码器电路的紧凑型无毛刺M

    公开(公告)号：US5327128A

    公开(公告)日：1994-07-05

    申请号：US007893

    申请日：1993-01-22

    Applicant: Man S. Lee

    Inventor： Man S. Lee

    IPC: H03M7/00 ,  H03M7/20

    CPC classification number: H03M7/005 ,  H03M7/20

    Abstract: An M of N decoder circuit includes N output terminals, log.sub.2 (n+1) logic input terminals, two voltage input terminals, and (N+1)log.sub.2 (N+1) pass transistors, each having a gate connected to one of the logic input terminals, a source connected to one of a voltage input terminal and an output terminal, and a drain connected to one of said output terminals, each of the pass transistors for passing a voltage signal from source to drain when the gate has applied to it one logic level and for not passing said voltage signal when the gate has applied to a different logic level. More particularly, half of the pass transistors are of one conduction type and half of the pass transistors are of an opposite conduction type. The gates of N+1 pass transistors are connected to each of the log.sub.2 (M+1) input terminals. For i =0 to log.sub.2 (N+1)-1, pass transistors of one conduction type whose gates are connected to an i-th input terminal are connected in groups of 2.sup.i, and pass transistors of the opposite conduction type whose gates are connect to the i-th input terminal are also connected in groups of 2.sup.i.

    Abstract translation: N个解码器电路的M包括N个输出端子，log2（n + 1）逻辑输入端子，两个电压输入端子和（N + 1）个log2（N + 1）个传输晶体管，每个具有连接到 逻辑输入端子，连接到电压输入端子和输出端子之一的源极以及连接到所述输出端子之一的漏极，每个所述通过晶体管用于当栅极施加到栅极时将电压信号从源极传导到漏极 它是一个逻辑电平，并且当门施加到不同的逻辑电平时不通过所述电压信号。 更具体地说，一半的通过晶体管是一种导通型，而一半的通过晶体管具有相反的导通型。 N + 1传输晶体管的栅极连接到log2（M + 1）输入端子中的每一个。 对于i = 0到log2（N + 1）-1，将栅极连接到第i个输入端的一个导通型的通过晶体管以2i的组连接，并且栅极连接的相反导电类型的通过晶体管 到第i个输入端子也以2i组连接。

    Digit regeneration in two-out-of-five format code systems
    10.
    发明授权
    Digit regeneration in two-out-of-five format code systems 失效
    二进制格式代码系统中的数字再生

    公开(公告)号：US3883857A

    公开(公告)日：1975-05-13

    申请号：US45658574

    申请日：1974-04-01

    Applicant: GTE AUTOMATIC ELECTRIC LAB INC

    Inventor： MAGNUSSON STIG E

    IPC: H03M7/20 ,  H03M7/30 ,  G11C13/00

    CPC classification number: H03M7/30 ,  H03M7/20

    Abstract: A technique for utilizing memories having word lengths of four bits in a system employing a two-out-of five code format. Four digits only are stored with the fifth digit regenerated on readout by logic circuitry connected in parallel to the memory system readout.

    Abstract translation: 一种在采用五进制码格式的系统中利用具有四位字长的存储器的技术。 仅存储四位数字，第五位数字通过与存储器系统读数并行连接的逻辑电路在读出时再生。

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