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1.发明授权Quasi-surrounding gate and a method of fabricating a silicon-on-insulator semiconductor device with the same 有权准周围栅极及其制造上述绝缘体上硅的半导体器件的方法公开(公告)号：US06359311B1
公开(公告)日：2002-03-19
申请号：US09761889
申请日：2001-01-17
IPC分类号： H01L2701
CPC分类号： H01L29/42384 , H01L29/66795 , H01L29/7854
摘要： The present invention discloses a method of fabricating a SOI semiconductor device with a quasi surrounding gate in the silicon substrate to increase the device current per unit device width, and allows better control over the short-channel effect and sub-threshold leakage. This method also enables fabrication of variable gate-length devices using conventional techniques compared to vertical/pillar transistors.
摘要翻译： 本发明公开了一种在硅衬底中制造具有准周围栅极的SOI半导体器件的方法，以增加每单位器件宽度的器件电流，并且允许更好地控制短沟道效应和次阈值泄漏。 与垂直/立柱晶体管相比，该方法还能够使用常规技术制造可变栅极长度器件。
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2.发明授权Method of fabricating a silicon-on-insulator semiconductor device with an implanted ground plane 有权一种具有植入接地层的绝缘体上硅半导体器件的制造方法公开(公告)号：US06391752B1
公开(公告)日：2002-05-21
申请号：US09659920
申请日：2000-09-12
IPC分类号： H01L213205
CPC分类号： H01L29/66583 , H01L21/2652 , H01L27/1203 , H01L29/66553 , H01L29/66772 , H01L29/78648
摘要： A method of fabricating a SOI semiconductor device with an implanted ground plane in the silicon substrate to increase the doping concentration underneath the channel region for suppressing short-channel effects (SCEs) such as drain-induced barrier lowering (DIBL). For a N-channel MOSFET, the implanted ground plane is P+ type such that if a P-type underlying substrate is used, the ground plane is automatically connected to ground potential (the substrate potential). For a SOI-type CMOS semiconductor device with two spaced-apart implanted ground planes each self-aligned to be underneath a corresponding channel region of the CMOS, two SOI-type MOSFET semiconductor devices of opposite conductivity types are formed on a same semiconductor substrate. The increase in doping concentration underneath the channel region prevents the electric field lines from the gate from terminating under the channel region; instead, the electric field lines terminate in the ground plane, thereby suppressing the short-channel effects and the off-state leakage current of the MOSFETs.
摘要翻译： 一种在硅衬底中制造具有注入接地面的SOI半导体器件的方法，以增加沟道区下方的掺杂浓度，以抑制诸如漏极诱导的势垒降低（DIBL）的短沟道效应（SCE）。 对于N沟道MOSFET，注入接地层是P +型，使得如果使用P型底层衬底，则接地层自动连接到接地电位（衬底电位）。 对于具有两个间隔开的注入接地层的SOI型CMOS半导体器件，其每个自对准位于CMOS的相应沟道区的下方，在同一半导体衬底上形成两个相反导电类型的SOI型MOSFET半导体器件。 通道区域下面的掺杂浓度的增加阻止了来自栅极的电场线在沟道区域下结束; 电场线终止于接地面，从而抑制MOSFET的短路效应和截止状态的漏电流。
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