公开(公告)号：US20080259221A1

公开(公告)日：2008-10-23

申请号：US12106220

申请日：2008-04-18

申请人： Jean-Claude Longchambon ,  Jean Nivet ,  Denis Dutoit

发明人： Jean-Claude Longchambon ,  Jean Nivet ,  Denis Dutoit

IPC分类号： H04N5/66 ,  G06F13/38 ,  G06F13/12

CPC分类号： H04N21/23602 ,  H04M1/72527 ,  H04N21/4122 ,  H04N21/4126 ,  H04N21/41407 ,  H04N21/4342 ,  H04N21/43632 ,  H04N21/4402 ,  H04N2201/0034 ,  H04N2201/0065 ,  H04N2201/0096

摘要： Circuitry for providing an output video signal from a portable device to an external display, the circuitry including a processor block with an image processor, and a video encoder block with a video encoder for providing the output video signal to the external display, the processor block and the video encoder block being connected to each other by a serial interface arranged to provide image date from the processor block to the video encoder, the serial interface having at least one data lane and at least one first clock lane, wherein the video encoder block includes a first input connected to the at least one data lane for receiving image data and a second input connected to the at least one first clock lane for receiving a first clock signal, and wherein at least one of the video encoder block and the processor block has a third input arranged to receive a control signal for controlling data flow over the serial interface.

摘要翻译： 用于从便携式设备向外部显示器提供输出视频信号的电路，所述电路包括具有图像处理器的处理器块，以及具有用于将输出视频信号提供给外部显示器的视频编码器的视频编码器块，处理器块 并且所述视频编码器块通过布置成从所述处理器块提供图像日期到所述视频编码器的串行接口彼此连接，所述串行接口具有至少一个数据通道和至少一个第一时钟通道，其中所述视频编码器块 包括连接到所述至少一个用于接收图像数据的数据通道的第一输入和连接到所述至少一个第一时钟通道以用于接收第一时钟信号的第二输入，并且其中所述视频编码器块和所述处理器块中的至少一个 具有布置成接收用于控制串行接口上​​的数据流的控制信号的第三输入。

公开(公告)号：US20060176748A1

公开(公告)日：2006-08-10

申请号：US11346796

申请日：2006-02-03

申请人： Francois Druilhe ,  Andrew Cofler ,  Denis Dutoit ,  Michel Harrand ,  Gilles Eyzat ,  Christian Freund

发明人： Francois Druilhe ,  Andrew Cofler ,  Denis Dutoit ,  Michel Harrand ,  Gilles Eyzat ,  Christian Freund

IPC分类号： G11C7/00

CPC分类号： G11C11/406 ,  G11C2211/4061 ,  G11C2211/4067

摘要： A DRAM and its application to a mobile telephony circuit with a control circuit including a first refreshment controller controlled by a first clock signal and a second refreshment controller controlled by a second clock signal having a frequency less than that of the first one and used to synchronize events of the GSM network.

公开(公告)号：US07486582B2

公开(公告)日：2009-02-03

申请号：US11346796

申请日：2006-02-03

申请人： François Druilhe ,  Andrew Cofler ,  Denis Dutoit ,  Michel Harrand ,  Gilles Eyzat ,  Christian Freund

发明人： François Druilhe ,  Andrew Cofler ,  Denis Dutoit ,  Michel Harrand ,  Gilles Eyzat ,  Christian Freund

IPC分类号： G11C7/00

CPC分类号： G11C11/406 ,  G11C2211/4061 ,  G11C2211/4067

摘要： A DRAM and its application to a mobile telephony circuit with a control circuit including a first refreshment controller controlled by a first clock signal and a second refreshment controller controlled by a second clock signal having a frequency less than that of the first one and used to synchronize events of the GSM network.

摘要翻译： 一种DRAM及其在具有控制电路的移动电话电路中的应用，该控制电路包括由第一时钟信号控制的第一更新控制器和由具有小于第一时钟信号频率的第二时钟信号控制的第二更新控制器，并且用于同步 GSM网络的事件。