公开(公告)号：US07370182B2

公开(公告)日：2008-05-06

申请号：US10082816

申请日：2002-02-25

申请人： Andrew Cofler ,  Anne Merlande ,  Sebastien Ferroussat

发明人： Andrew Cofler ,  Anne Merlande ,  Sebastien Ferroussat

IPC分类号： G06F7/38 ,  G06F9/00 ,  G06F9/44 ,  G06F15/00

CPC分类号： G06F9/3804 ,  G06F9/30094 ,  G06F9/3836 ,  G06F9/3842

摘要： A processor includes a program memory containing program instructions, and a processor core including several processing units and a central unit. The central unit, upon receipt of a program instruction, issues corresponding instructions to the various processing units. The processor core is clocked by a clock signal. A branching instruction received by the central unit, in the course of a current cycle, is processed in the course of the current cycle.

摘要翻译： 处理器包括包含程序指令的程序存储器和包括若干处理单元和中央单元的处理器核心。 中央单元在接收到程序指令时，向各种处理单元发出相应的指令。 处理器内核由时钟信号计时。 在当前周期的过程中，由中央单元接收的分支指令在当前周期的过程中被处理。

公开(公告)号：US07111152B1

公开(公告)日：2006-09-19

申请号：US09563704

申请日：2000-05-02

申请人： Andrew Cofler ,  Bruno Fel ,  Laurent Ducousso

发明人： Andrew Cofler ,  Bruno Fel ,  Laurent Ducousso

IPC分类号： G06F9/30

CPC分类号： G06F9/3838 ,  G06F9/3836 ,  G06F9/3853 ,  G06F9/3857

摘要： Instructions in a computer system are executed in a plurality of parallel execution pipelines, a horizontal dependency check is carried out between instructions supplied to the parallel pipelines and in response to detecting horizontal dependency a control signal of a first or second type is generated depending on whether the dependency can be resolved by activating a by-pass or whether a temporary stall is required in one of the pipelines.

摘要翻译： 在多个并行执行流水线中执行计算机系统中的指令，在提供给并行流水线的指令之间执行水平依赖性检查，并且响应于检测水平依赖性，根据是否产生第一或第二类型的控制信号 可以通过激活旁路或者在其中一条管道中是否需要临时停顿来解决依赖关系。

公开(公告)号：US20050251661A1

公开(公告)日：2005-11-10

申请号：US11031956

申请日：2005-01-07

申请人： Laurent Uguen ,  Sebastien Ferroussat ,  Andrew Cofler ,  Thomas Alofs

发明人： Laurent Uguen ,  Sebastien Ferroussat ,  Andrew Cofler ,  Thomas Alofs

IPC分类号： G06F9/00 ,  G06F9/38

CPC分类号： G06F9/3885 ,  G06F9/30072 ,  G06F9/30094 ,  G06F9/30101 ,  G06F9/3838

摘要： A method of transferring guard values and a computer system, such as a processor for digital signal processing, including a parallel set of execution units that utilizes the method. A master set of guard indicators is held in association with one of the execution units. If other execution units require the guard values for particular guard indicators, a sendguard instruction is issued to the execution unit holding the master guard values. The sendguard instructions are held in a separate queue from the main instructions intended for that execution unit. Circuitry is provided in the execution unit to avoid stalling in the dispatch of sendguard instructions even in the context of earlier guard modifying instructions.

摘要翻译： 传送保护值的方法和诸如用于数字信号处理的处理器的计算机系统，包括利用该方法的一组并行执行单元。 与其中一个执行单元相关联地保存有一组主要的保护指示符。 如果其他执行单元需要特定保护指示灯的保护值，则将发送保护指令给持有主保护值的执行单元。 sendguard指令被保存在与该执行单元的主要指令的单独队列中。 在执行单元中提供电路，以避免即使在前面的保护修改指令的上下文中发送发送指令的停止。

公开(公告)号：US06959379B1

公开(公告)日：2005-10-25

申请号：US09562542

申请日：2000-05-02

申请人： Laurent Wojcieszak ,  Andrew Cofler

发明人： Laurent Wojcieszak ,  Andrew Cofler

IPC分类号： G06F9/30 ,  G06F9/32 ,  G06F9/38 ,  G06F15/00

CPC分类号： G06F9/381 ,  G06F9/30149 ,  G06F9/325

摘要： A method of executing loops in a computer system is described. The computer system has a sequence of instructions held in program memory and a prefetch buffer which holds instructions fetched from the memory ready for supply to a decoder of the computer system. If the size of the loop to be executed is such that it can by holly contained within the prefetch buffer, this is detected and a lock is put on the prefetch buffer to retain the loop within it while the loop is executed a requisite number of times. This thus allows power to be saved and reduces the overhead on the memory access buffers. According to another aspect, loops can be “skipped” by holding a value of zero in the loop counter register.

摘要翻译： 描述了在计算机系统中执行循环的方法。 计算机系统具有保存在程序存储器中的指令序列和保存从存储器取出的指令的预取缓冲器，准备供给计算机系统的解码器。 要执行的循环的大小使得它可以通过冬青包含在预取缓冲器中，这被检测到，并且锁定放在预取缓冲器上以将循环保持在其中，同时循环被执行必要的次数 。 这因此允许保存电力并减少存储器访问缓冲器的开销。 根据另一方面，可以通过在循环计数器寄存器中保持零值来“跳过”循环。

公开(公告)号：US20060184775A1

公开(公告)日：2006-08-17

申请号：US11384024

申请日：2006-03-17

申请人： Andrew Cofler ,  Laurent Wojcieszak ,  Isabelle Sename

发明人： Andrew Cofler ,  Laurent Wojcieszak ,  Isabelle Sename

IPC分类号： G06F9/44

CPC分类号： G06F11/3656 ,  G06F9/3842

摘要： A computer system with enhanced integrated debug facilities is described. According to one aspect, step-by-step execution of an instruction sequence is implemented where each instruction is guarded. If, after guard resolution, the instruction is committed, a divert routine is executed. If the instruction is not committed, the next instruction in the sequence is executed. According to another aspect, a stall state can be set at the decode unit either by reading stall attributes associated with debug instructions, or responsive to a stall command from an on-chip emulation unit.

摘要翻译： 描述了一种具有增强型集成调试功能的计算机系统。 根据一个方面，执行指令序列的逐步执行，其中每个指令被保护。 如果在保护解决之后，执行指令，则执行转移程序。 如果指令未提交，则执行该顺序中的下一条指令。 根据另一方面，可以通过读取与调试指令相关联的失速属性，或响应来自片上仿真单元的失速命令，在解码单元处设置失速状态。

公开(公告)号：US06711668B1

公开(公告)日：2004-03-23

申请号：US09562718

申请日：2000-05-02

申请人： Laurent Wojcieszak ,  Andrew Cofler

发明人： Laurent Wojcieszak ,  Andrew Cofler

IPC分类号： G06F938

CPC分类号： G06F9/3814 ,  G06F9/30149 ,  G06F9/30181 ,  G06F9/30189 ,  G06F9/3802 ,  G06F9/3853

摘要： A prefetch buffer is described which supports a computer system having a plurality of different instruction modes. The number of storage locations which are read out of the prefetch buffer during each machine cycle is controlled in dependence on the instruction mode. Thus the prefetch buffer allows a number of different instruction modes to be support and hides memory access latency.

摘要翻译： 描述了一种预取缓冲器，其支持具有多个不同指令模式的计算机系统。 根据指令模式控制在每个机器周期期间从预取缓冲器中读出的存储位置的数量。 因此，预取缓冲器允许支持多种不同的指令模式并隐藏存储器访问等待时间。

公开(公告)号：US5848109A

公开(公告)日：1998-12-08

申请号：US510458

申请日：1995-08-02

申请人： Roland Marbot ,  Jean-Claude Le Bihan ,  Andrew Cofler ,  Anne Pierre Duplessix ,  Pascal Couteaux ,  Reza Nezamzadeh-Moosavi

发明人： Roland Marbot ,  Jean-Claude Le Bihan ,  Andrew Cofler ,  Anne Pierre Duplessix ,  Pascal Couteaux ,  Reza Nezamzadeh-Moosavi

IPC分类号： H04L7/00 ,  H04L7/033 ,  H03B3/04

CPC分类号： H04L7/0337 ,  H04L7/0029

摘要： A process and apparatus for sampling a serial digital signal (D), which includes phasing of the digital signal with a clock signal (C) and sampling the digital signal at delayed instants (Si), wherein the phasing is carried out in reference to the sampling instants. The phasing includes determining phasing test instants (Pi) which refer to the sampling instants (Si) to verify whether transitions of the digital signal are leading or lagging in phase relative to the phasing test instants. The determination of the phasing test instants is achieved by adding to each sampling instant (Si) a delay Y=kR/2, in which k is a positive whole odd number other than zero and R designates a pulse repetition period of the bits of the digital signal (D). The invention has particular utility in data processing and remote data processing systems, and to telecommunication systems.

摘要翻译： 一种用于对串行数字信号（D）进行采样的处理和装置，其包括用时钟信号（C）对数字信号进行定相并在延迟时刻（Si）对数字信号进行采样，其中定相参照 抽样时刻。 定相包括确定参考采样时刻（Si）的相位测试时刻（Pi），以验证数字信号的转换是相对于定相测试时刻是在前进还是相位滞后。 定相测试时刻的确定是通过将​​延迟Y = kR / 2加到每个采样时刻（Si）来实现的，其中k是除零之外的正整数奇数，R表示 数字信号（D）。 本发明在数据处理和远程数据处理系统以及电信系统中具有特别的用途。

公开(公告)号：US07496737B2

公开(公告)日：2009-02-24

申请号：US11031956

申请日：2005-01-07

申请人： Laurent Uguen ,  Sébastien Ferroussat ,  Andrew Cofler ,  Thomas Alofs

发明人： Laurent Uguen ,  Sébastien Ferroussat ,  Andrew Cofler ,  Thomas Alofs

IPC分类号： G06F9/00

CPC分类号： G06F9/3885 ,  G06F9/30072 ,  G06F9/30094 ,  G06F9/30101 ,  G06F9/3838

摘要： A method of transferring guard values and a computer system, such as a processor for digital signal processing, including a parallel set of execution units that utilizes the method. A master set of guard indicators is held in association with one of the execution units. If other execution units require the guard values for particular guard indicators, a sendguard instruction is issued to the execution unit holding the master guard values. The sendguard instructions are held in a separate queue from the main instructions intended for that execution unit. Circuitry is provided in the execution unit to avoid stalling in the dispatch of sendguard instructions even in the context of earlier guard modifying instructions.

摘要翻译： 传送保护值的方法和诸如用于数字信号处理的处理器的计算机系统，包括利用该方法的一组并行执行单元。 与其中一个执行单元相关联地保存有一组主要的保护指示符。 如果其他执行单元需要特定保护指示灯的保护值，则将发送保护指令给持有主保护值的执行单元。 sendguard指令被保存在与该执行单元的主要指令的单独队列中。 在执行单元中提供电路，以避免即使在前面的保护修改指令的上下文中发送发送指令的停止。

公开(公告)号：US07290089B2

公开(公告)日：2007-10-30

申请号：US10270753

申请日：2002-10-15

申请人： Sivagnanam Parthasarathy ,  Andrew Cofler ,  Lionel Chaverot

发明人： Sivagnanam Parthasarathy ,  Andrew Cofler ,  Lionel Chaverot

IPC分类号： G06F12/00

CPC分类号： G06F9/381 ,  G06F9/30181 ,  G06F9/325 ,  G06F9/3875 ,  G06F12/0864 ,  G06F12/0877 ,  G06F2212/1028 ,  Y02D10/13

摘要： For instruction clusters for which no significant performance penalty is incurred, such as execution of hardware loops, a processor automatically and dynamically switches to a pipelined two-cycle access to an associated associative cache rather than a single-cycle access. An access involving more than one cycle uses less power because only the hit way within the cache memory is accessed rather than all ways within the indexed cache line. To maintain performance, the single-cycle cache access is utilized in all remaining instructions. In addition, where instruction clusters within a hardware loop fit entirely within a pre-fetch buffer, the cache sub-system is idled for any remaining iterations of the hardware loop to further reduce power consumption.

摘要翻译： 对于不会产生显着性能损失（如执行硬件循环）的指令集，处理器自动和动态切换到流水线的两周期访问关联的关联高速缓存而不是单周期访问。 涉及多个周期的访问使用更少的功率，因为​​只有高速缓存中的命中方式被访问，而不是索引的高速缓存行内的所有方式。 为了保持性能，在所有剩余指令中使用单周期高速缓存访​​问。 此外，在硬件环路内的指令集合完全适合预取缓冲器的情况下，高速缓存子系统对于硬件循环的任何剩余迭代而空闲以进一步降低功耗。

公开(公告)号：US07013256B2

公开(公告)日：2006-03-14

申请号：US10021269

申请日：2001-12-12

申请人： Andrew Cofler ,  Laurent Wojcieszak ,  Arnaud Dehamel ,  Isabelle Sename

发明人： Andrew Cofler ,  Laurent Wojcieszak ,  Arnaud Dehamel ,  Isabelle Sename

IPC分类号： G06F9/455 ,  G06F11/36

CPC分类号： G06F11/3632 ,  G06F9/30072 ,  G06F11/3648

摘要： A computer system for executing instructions having assigned guard indicators, comprises instruction supply circuitry, pipelined execution units for receiving instructions from the supply circuitry together with at least one guard indicator selected from a set of guard indicators, the execution unit including a master guard value store containing master values for the guard indicators, and circuitry for resolving the guard values in the execution pipeline and providing a signal to indicate whether the pipeline is committed to the execution of the instruction, and an emulator having watch circuitry for effecting a watch on selected instructions supplied to the execution pipeline and synchronising circuitry for correlating resolution of the guard indicator of each selected instruction with a program count for that instruction.