公开(公告)号：US07080365B2

公开(公告)日：2006-07-18

申请号：US10113582

申请日：2002-03-29

申请人： Jeffrey M. Broughton ,  Liang T. Chen ,  William kwei-cheung Lam ,  Derek E. Pappas ,  Ihao Chen ,  Thomas M. McWilliams ,  Ankur Narang ,  Jeffrey B. Rubin ,  Earl T. Cohen ,  Michael W. Parkin ,  Ashley N. Saulsbury ,  Michael S. Ball

发明人： Jeffrey M. Broughton ,  Liang T. Chen ,  William kwei-cheung Lam ,  Derek E. Pappas ,  Ihao Chen ,  Thomas M. McWilliams ,  Ankur Narang ,  Jeffrey B. Rubin ,  Earl T. Cohen ,  Michael W. Parkin ,  Ashley N. Saulsbury ,  Michael S. Ball

IPC分类号： G06F9/45

CPC分类号： G06F17/5022 ,  G06F8/427 ,  G06F8/443 ,  G06F8/445 ,  G06F8/45

摘要： A method for compiling a cycle-based design involves generating a parsed cycle-based design from the cycle-based design, elaborating the parsed cycle-based design to an annotated syntax tree, translating the annotated syntax tree to an intermediate form, and converting the intermediate form to an executable form.

公开(公告)号：US07036114B2

公开(公告)日：2006-04-25

申请号：US10113005

申请日：2002-03-29

申请人： Thomas M. McWilliams ,  Jeffrey B. Rubin ,  Derek E. Pappas ,  Oyekunle A. Olukotun ,  Jeffrey M. Broughton ,  David R. Emberson ,  William kwei-cheung Lam ,  Liang T. Chen ,  Ihao Chen ,  Earl T. Cohen ,  Michael W. Parkin

发明人： Thomas M. McWilliams ,  Jeffrey B. Rubin ,  Derek E. Pappas ,  Oyekunle A. Olukotun ,  Jeffrey M. Broughton ,  David R. Emberson ,  William kwei-cheung Lam ,  Liang T. Chen ,  Ihao Chen ,  Earl T. Cohen ,  Michael W. Parkin

IPC分类号： G06F9/45

CPC分类号： G06F17/5022 ,  G06F2217/68

摘要： A computer system for cycle-based computation includes a processor array, a translation component adapted to translate a cycle-based design, a host computer operatively connected to the processor array and to the translation component, a data connection component interconnecting a plurality of members of the processor array using static routing, a synchronization component enabling known timing relationships among the plurality of members of the processor array, a host service request component adapted to send a host service request from a member of the processor array to the host computer, and an access component adapted to access a portion of a state of the processor array and a portion of a state of the data connection.

公开(公告)号：US07076416B2

公开(公告)日：2006-07-11

申请号：US10105754

申请日：2002-03-25

申请人： Liang T. Chen ,  William kwei-cheung Lam ,  Thomas M. McWilliams

发明人： Liang T. Chen ,  William kwei-cheung Lam ,  Thomas M. McWilliams

IPC分类号： G06F17/50

CPC分类号： G06F17/5022

摘要： A method for evaluating a logic state of a design node involves compiling a logic design to generate an annotated symbol table and a levelized design, obtaining a logic evaluation cost from the levelized design, locating a strategic node using the logic evaluation cost, marking the strategic node, and computing the logic state of the design node using the annotated symbol table, the strategic node, and the levelized design.

摘要翻译： 用于评估设计节点的逻辑状态的方法包括编译逻辑设计以生成注释符号表和级别化设计，从级别化设计获得逻辑评估成本，使用逻辑评估成本来定位策略节点，标记战略 节点，并使用注释符号表，策略节点和级别化设计来计算设计节点的逻辑状态。