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1.发明授权System and method to provide non-coherent access to a coherent memory system 有权提供对相干存储器系统的非相干访问的系统和方法公开(公告)号：US08850125B2
公开(公告)日：2014-09-30
申请号：US13280756
申请日：2011-10-25
CPC分类号： G06F12/0888 , G06F12/08 , G06F12/0831
摘要： In one embodiment, a system comprises a memory and a memory controller that provides a cache access path to the memory and a bypass-cache access path to the memory, receives requests to read graph data from the memory on the bypass-cache access path and receives requests to read non-graph data from the memory on the cache access path. A method comprises receiving a request at a memory controller to read graph data from a memory on a bypass-cache access path, receiving a request at the memory controller to read non-graph data from the memory through a cache access path, and arbitrating, in the memory controller, among the requests using arbitration.
摘要翻译： 在一个实施例中，系统包括存储器和存储器控制器，其提供到存储器的高速缓存访问路径和到存储器的旁路高速缓存访问路径，接收从旁路高速缓存访问路径上的存储器读取图形数据的请求，以及 接收从缓存访问路径上的内存中读取非图形数据的请求。 一种方法包括在存储器控制器处接收来自旁路高速缓存访问路径上的存储器的图形数据的请求，在存储器控制器处接收请求以通过高速缓存访问路径从存储器读取非图形数据， 在内存控制器中，在使用仲裁的请求中。
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2.发明申请SYSTEM AND METHOD TO PROVIDE NON-COHERENT ACCESS TO A COHERENT MEMORY SYSTEM 有权提供对相关存储器系统的非相互访问的系统和方法公开(公告)号：US20130103909A1
公开(公告)日：2013-04-25
申请号：US13280756
申请日：2011-10-25
IPC分类号： G06F12/08
CPC分类号： G06F12/0888 , G06F12/08 , G06F12/0831
摘要： In one embodiment, a system comprises a memory and a memory controller that provides a cache access path to the memory and a bypass-cache access path to the memory, receives requests to read graph data from the memory on the bypass-cache access path and receives requests to read non-graph data from the memory on the cache access path. A method comprises receiving a request at a memory controller to read graph data from a memory on a bypass-cache access path, receiving a request at the memory controller to read non-graph data from the memory through a cache access path, and arbitrating, in the memory controller, among the requests using arbitration.
摘要翻译： 在一个实施例中，系统包括存储器和存储器控制器，其提供到存储器的高速缓存访问路径和到存储器的旁路高速缓存访问路径，接收从旁路高速缓存访问路径上的存储器读取图形数据的请求，以及 接收从缓存访问路径上的内存中读取非图形数据的请求。 一种方法包括在存储器控制器处接收来自旁路高速缓存访问路径上的存储器的图形数据的请求，在存储器控制器处接收请求以通过高速缓存访问路径从存储器读取非图形数据， 在内存控制器中，在使用仲裁的请求中。
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3.发明授权System and method to reduce memory access latencies using selective replication across multiple memory ports 有权使用多个内存端口选择性复制来减少内存访问延迟的系统和方法公开(公告)号：US08560757B2
公开(公告)日：2013-10-15
申请号：US13280738
申请日：2011-10-25
IPC分类号： G06F12/00
CPC分类号： G06F12/1018 , G06F12/0292 , G06F12/06 , G06F2212/174 , G06F2212/2532
摘要： In one embodiment, a system includes memory ports distributed into subsets identified by a subset index, where each memory port has an individual wait time based on a respective workload. The system further comprises a first address hashing unit configured to receive a read request including a virtual memory address associated with a replication factor and referring to graph data. The first address hashing unit translates the replication factor into a corresponding subset index based on the virtual memory address, and converts the virtual memory address to a hardware based memory address referring to graph data in the memory ports within a subset indicated by the corresponding subset index. The system further comprises a memory replication controller configured to direct read requests to the hardware based address to the one of the memory ports within the subset indicated by the corresponding subset index with a lowest individual wait time.
摘要翻译： 在一个实施例中，系统包括分布到由子集索引识别的子集中的存储器端口，其中每个存储器端口基于相应的工作负载具有单独的等待时间。 该系统还包括第一地址哈希单元，其被配置为接收包括与复制因子相关联的虚拟存储器地址并参考图形数据的读取请求。 第一地址散列单元基于虚拟存储器地址将复制因子转换为相应的子集索引，并且参考由相应子集索引指示的子集内的存储器端口中的图形数据将虚拟存储器地址转换为基于硬件的存储器地址 。 该系统还包括存储器复制控制器，其被配置为将读取请求引导到基于硬件的地址到具有最低个人等待时间的相应子集索引指示的子集内的存储器端口之一。
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4.发明申请SYSTEM AND METHOD TO REDUCE MEMORY ACCESS LATENCIES USING SELECTIVE REPLICATION ACROSS MULTIPLE MEMORY PORTS 有权使用多个存储器端口选择性复制来减少存储器访问延迟的系统和方法公开(公告)号：US20130103904A1
公开(公告)日：2013-04-25
申请号：US13280738
申请日：2011-10-25
CPC分类号： G06F12/1018 , G06F12/0292 , G06F12/06 , G06F2212/174 , G06F2212/2532
摘要： In one embodiment, a system comprises multiple memory ports distributed into multiple subsets, each subset identified by a subset index and each memory port having an individual wait time. The system further comprises a first address hashing unit configured to receive a read request including a virtual memory address associated with a replication factor, and referring to graph data. The first address hashing unit translates the replication factor into a corresponding subset index based on the virtual memory address, and converts the virtual memory address to a hardware based memory address that refers to graph data in the memory ports within a subset indicated by the corresponding subset index. The system further comprises a memory replication controller configured to direct read requests to the hardware based address to the one of the memory ports within the subset indicated by the corresponding subset index with a lowest individual wait time.
摘要翻译： 在一个实施例中，系统包括分布到多个子集中的多个存储器端口，每个子集由子集索引标识，每个存储器端口具有单独的等待时间。 该系统还包括第一地址哈希单元，其被配置为接收包括与复制因子相关联的虚拟存储器地址的读取请求，并且参考图形数据。 第一地址散列单元基于虚拟存储器地址将复制因子转换为对应的子集索引，并将虚拟存储器地址转换为基于硬件的存储器地址，该存储器地址涉及由相应子集指示的子集内的存储器端口中的图形数据 指数。 该系统还包括存储器复制控制器，其被配置为将读取请求引导到基于硬件的地址到具有最低个人等待时间的相应子集索引指示的子集内的存储器端口之一。
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公开(公告)号：US08977944B2
公开(公告)日：2015-03-10
申请号：US13325943
申请日：2011-12-14
CPC分类号： G06F11/1004 , G06F11/1016 , G06F11/1076 , H03M13/09
摘要： In one embodiment, a system includes a memory, and a memory controller coupled to the memory via an address bus, a data bus, and an error code bus. The memory stores data at an address and stores an error code at the address. The error code is generated based on a function of the corresponding data and address.
摘要翻译： 在一个实施例中，系统包括存储器，以及经由地址总线，数据总线和错误代码总线耦合到存储器的存储器控制器。 存储器将数据存储在地址处，并在地址处存储错误代码。 基于相应数据和地址的函数生成错误代码。
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公开(公告)号：US20130097608A1
公开(公告)日：2013-04-18
申请号：US13274767
申请日：2011-10-17
IPC分类号： G06F9/46
CPC分类号： G06F9/5027 , G06F9/4881 , G06F2209/509
摘要： Work submitted to a co-processor enters through one of multiple input queues, used to provide various quality of service levels. In-memory linked-lists store work to be performed by a network services processor in response to lack of processing resources in the network services processor. The work is moved back from the in-memory inked-lists to the network services processor in response to availability of processing resources in the network services processor.
摘要翻译： 提交给协处理器的工作通过多个输入队列之一进入，用于提供各种服务质量水平。 内存链接列表存储由网络服务处理器执行的工作，以响应网络服务处理器中的处理资源的缺乏。 响应于网络服务处理器中的处理资源的可用性，将工作从内存中墨迹列表移回到网络服务处理器。
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公开(公告)号：US09465662B2
公开(公告)日：2016-10-11
申请号：US13274767
申请日：2011-10-17
CPC分类号： G06F9/5027 , G06F9/4881 , G06F2209/509
摘要： Work submitted to a co-processor enters through one of multiple input queues, used to provide various quality of service levels. In-memory linked-lists store work to be performed by a network services processor in response to lack of processing resources in the network services processor. The work is moved back from the in-memory inked-lists to the network services processor in response to availability of processing resources in the network services processor.
摘要翻译： 提交给协处理器的工作通过多个输入队列之一进入，用于提供各种服务质量水平。 内存链接列表存储由网络服务处理器执行的工作，以响应网络服务处理器中的处理资源的缺乏。 响应于网络服务处理器中的处理资源的可用性，将工作从内存中墨迹列表移回到网络服务处理器。
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公开(公告)号：US20120185752A1
公开(公告)日：2012-07-19
申请号：US13325943
申请日：2011-12-14
CPC分类号： G06F11/1004 , G06F11/1016 , G06F11/1076 , H03M13/09
摘要： In one embodiment, a system includes a memory, and a memory controller coupled to the memory via an address bus, a data bus, and an error code bus. The memory stores data at an address and stores an error code at the address. The error code is generated based on a function of the corresponding data and address.
摘要翻译： 在一个实施例中，系统包括存储器，以及经由地址总线，数据总线和错误代码总线耦合到存储器的存储器控制器。 存储器将数据存储在地址处，并在地址处存储错误代码。 基于相应数据和地址的函数生成错误代码。
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公开(公告)号：US07594081B2
公开(公告)日：2009-09-22
申请号：US11024002
申请日：2004-12-28
CPC分类号： G06F9/3824 , G06F9/3885 , G06F12/0888
摘要： A content aware application processing system is provided for allowing directed access to data stored in a non-cache memory thereby bypassing cache coherent memory. The processor includes a system interface to cache coherent memory and a low latency memory interface to a non-cache coherent memory. The system interface directs memory access for ordinary load/store instructions executed by the processor to the cache coherent memory. The low latency memory interface directs memory access for non-ordinary load/store instructions executed by the processor to the non-cache memory, thereby bypassing the cache coherent memory. The non-ordinary load/store instruction can be a coprocessor instruction. The memory can be a low-latency type memory. The processor can include a plurality of processor cores.
摘要翻译： 提供内容感知应用处理系统，用于允许定向访问存储在非高速缓冲存储器中的数据，从而绕过高速缓存一致存储器。 该处理器包括用于缓存相干存储器的系统接口和用于非高速缓存一致记忆体的低延迟存储器接口。 系统接口将由处理器执行的普通加载/存储指令的存储器访问指向高速缓存一致存储器。 低延迟存储器接口将由处理器执行的非普通加载/存储指令的存储器访问引导到非高速缓存存储器，从而绕过高速缓存一致存储器。 非普通的加载/存储指令可以是协处理器指令。 存储器可以是低延迟型存储器。 处理器可以包括多个处理器核。
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公开(公告)号：US07558925B2
公开(公告)日：2009-07-07
申请号：US11335189
申请日：2006-01-18
IPC分类号： G06F12/02
CPC分类号： G06F12/06 , G06F12/0653 , G06F2212/174
摘要： Methods and apparatus are provided for selectively replicating a data structure in a low-latency memory. The memory includes multiple individual memory banks configured to store replicated copies of the same data structure. Upon receiving a request to access the stored data structure, a low-latency memory access controller selects one of the memory banks, then accesses the stored data from the selected memory bank. Selection of a memory bank can be accomplished using a thermometer technique comparing the relative availability of the different memory banks. Exemplary data structures that benefit from the resulting efficiencies include deterministic finite automata (DFA) graphs and other data structures that are loaded (i.e., read) more often than they are stored (i.e., written).
摘要翻译： 提供了用于在低延迟存储器中选择性地复制数据结构的方法和装置。 存储器包括被配置为存储相同数据结构的复制副本的多个单独存储体。 在接收到访问所存储的数据结构的请求时，低延迟存储器访问控制器选择存储体之一，然后从所选存储体存取所存储的数据。 可以使用比较不同存储体的相对可用性的温度计技术来实现存储体的选择。 受益于所产生的效率的示例性数据结构包括确定性有限自动机（DFA）图和与它们被存储（即，写入）相比更加加载（即读）的其他数据结构。
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