公开(公告)号：US20190004967A1

公开(公告)日：2019-01-03

申请号：US15991241

申请日：2018-05-29

申请人： TEXAS INSTRUMENTS INCORPORATED

发明人： Abhijeet Ashok Chachad ,  Raguram Damodaran ,  Ramakrishnan Venkatasubramanian ,  Joseph Raymond Michael Zbiciak

IPC分类号： G06F12/1081 ,  G06F13/18 ,  H03K21/00 ,  G06F1/32 ,  G06F7/483 ,  G06F9/30 ,  G06F11/10 ,  H03M13/35 ,  G06F12/0811 ,  G06F12/0815 ,  G06F12/12 ,  G06F13/16 ,  H03M13/29 ,  H03K19/00 ,  G06F12/02 ,  G06F13/364

CPC分类号： G06F12/1081 ,  G06F1/3296 ,  G06F7/483 ,  G06F9/3012 ,  G06F11/1064 ,  G06F12/0246 ,  G06F12/0811 ,  G06F12/0815 ,  G06F12/12 ,  G06F13/1605 ,  G06F13/1652 ,  G06F13/1657 ,  G06F13/1663 ,  G06F13/18 ,  G06F13/364 ,  G06F2212/1021 ,  G06F2212/1032 ,  G06F2212/221 ,  G06F2212/2532 ,  G06F2212/283 ,  G06F2212/608 ,  H03K19/0016 ,  H03K21/00 ,  H03M13/2903 ,  H03M13/353 ,  Y02D10/124 ,  Y02D10/172 ,  Y02D50/20

摘要： A queuing requester for access to a memory system is provided. Transaction requests are received from two or more requestors for access to the memory system. Each transaction request includes an associated priority value. A request queue of the received transaction requests is formed in the queuing requester. Each transaction request includes an associated priority value. A highest priority value of all pending transaction requests within the request queue is determined. An elevated priority value is selected when the highest priority value is higher than the priority value of an oldest transaction request in the request queue; otherwise the priority value of the oldest transaction request is selected. The oldest transaction request in the request queue with the selected priority value is then provided to the memory system. An arbitration contest with other requesters for access to the memory system is performed using the selected priority value.

公开(公告)号：US20180307617A1

公开(公告)日：2018-10-25

申请号：US15493035

申请日：2017-04-20

申请人： Oracle International Corporation

发明人： Timothy L. Harris ,  David Dice

IPC分类号： G06F12/1009 ,  G06F12/14 ,  G06F12/1027

CPC分类号： G06F12/1009 ,  G06F12/1027 ,  G06F12/1433 ,  G06F2212/206 ,  G06F2212/2532 ,  G06F2212/65 ,  G06F2212/68

摘要： When performing non-sequential accesses to large data sets, hot spots may be avoided by permuting the memory locations being accesses to more evenly spread those accesses across the memory and across multiple memory channels. A permutation step may be used when accessing data, such as to improve the distribution of those memory accesses within the system. Instead of accessing one memory address, that address may be permuted so that another memory address is accessed. Non-sequential accesses to an array may be modified such that each index to the array is permuted to another index in the array. Collisions between pre- and post-translation addresses may be prevented and one-to-one mappings may be used. Permutation mechanisms may be implemented in software, hardware, or a combination of both, with or without the knowledge of the process performing the memory accesses.

公开(公告)号：US09940235B2

公开(公告)日：2018-04-10

申请号：US15197471

申请日：2016-06-29

申请人： Oracle International Corporation

发明人： Edward Alfonso Bucaro

IPC分类号： G06F17/00 ,  G06F12/06 ,  G06F13/40

CPC分类号： G06F12/0684 ,  G06F13/4068 ,  G06F2212/2532

摘要： Aspects of the present disclosure involve a system and method for verifying and validating accurate memory module placement on a printed circuit board. In one embodiment, the printed circuit board is configured to include actuating elements that can be used to verify correct memory module location placement on the printed circuit board. In another embodiment, the actuating elements can be used to validate accurate memory module placement. The actuating elements can be in the form of buttons that may be depressed and configured to trigger light emitting diodes (LEDs) that correspond to the slots on the printed circuit board.

公开(公告)号：US09921763B1

公开(公告)日：2018-03-20

申请号：US14750293

申请日：2015-06-25

申请人： Crossbar, Inc.

发明人： Cliff Zitlaw

IPC分类号： G06F3/06 ,  G11C14/00 ,  G06F12/06

CPC分类号： G06F3/0619 ,  G06F3/0665 ,  G06F3/0689 ,  G06F12/0623 ,  G06F2003/0692 ,  G06F2212/2532 ,  G11C7/1045 ,  G11C7/1063 ,  G11C7/22 ,  G11C8/12 ,  G11C13/00

摘要： Providing for a memory apparatus comprising multiple banks of non-volatile memory and a high-speed data bus is described herein. By way of example, the memory apparatus can employ a standard or near-standard DRAM bus as an interface to high-performance two-terminal memory arrays. Interleaved operation can facilitate throughputs over 2gigabytes/second, in various embodiments, and larger throughputs in at least some embodiments, by interleaving multiple memory banks that are separately addressed via one or more mode registers, referred to as an index register(s). Further, the memory apparatus can have one or two terabytes of total storage, with capacity to increase storage volume. According to various embodiments, the memory apparatus can operate with a standard DRAM controller, or a memory controller configured with a DRAM communication protocol, modified in software or firmware to match configurations of the non-volatile memory employed for the multiple banks of memory.

公开(公告)号：US09747041B2

公开(公告)日：2017-08-29

申请号：US14757926

申请日：2015-12-23

申请人： INTEL CORPORATION

发明人： Vedaraman Geetha ,  Henk G. Neefs ,  Brian S. Morris ,  Sreenivas Mandava ,  Massimo Sutera

IPC分类号： G06F12/00 ,  G06F3/06 ,  G06F12/0893 ,  G06F12/0866

CPC分类号： G06F3/0611 ,  G06F3/0638 ,  G06F3/068 ,  G06F12/0866 ,  G06F12/0893 ,  G06F2212/1021 ,  G06F2212/205 ,  G06F2212/2532 ,  G06F2212/45 ,  G06F2212/60

摘要： Provided are an apparatus and method for a non-power-of-2 size cache in a first level memory device to cache data present in a second level memory device having a 2n cache size. A request is to a target address having n bits directed to the second level memory device. A determination is made whether a target index, comprising m bits of the n bits of the target address, is within an index set of the first level memory device. A determination is made of a modified target index in the index set of the first level memory device having at least one index bit that differs from a corresponding at least one index bit in the target index. The request is processed with respect to data in a cache line at the modified target index in the first level memory device.

公开(公告)号：US09710173B2

公开(公告)日：2017-07-18

申请号：US14282467

申请日：2014-05-20

申请人： Micron Technology, Inc.

发明人： Eugene Feng ,  Mathew Arcoleo

IPC分类号： G06F3/06 ,  G06F12/08 ,  G11C29/44 ,  G06F12/10 ,  G11C7/10 ,  G06F12/0806 ,  G06F12/1081 ,  G11C29/00 ,  G06F13/28 ,  G06F12/0875 ,  G06F12/0888 ,  G11C29/04

CPC分类号： G06F3/0616 ,  G06F3/0608 ,  G06F3/0655 ,  G06F3/0685 ,  G06F3/0688 ,  G06F12/0806 ,  G06F12/0875 ,  G06F12/0888 ,  G06F12/1081 ,  G06F13/28 ,  G06F2212/2532 ,  G06F2212/621 ,  G11C7/1072 ,  G11C29/44 ,  G11C29/765 ,  G11C2029/0409 ,  G11C2207/2245 ,  Y02D10/13 ,  Y02D10/14

摘要： The present disclosure includes methods and apparatuses for read cache memory. One apparatus includes a read cache memory apparatus comprising a first DRAM array, a first and a second NAND array, and a controller configured to manage movement of data between the DRAM array and the first NAND array, and between the first NAND array and the second NAND array.

公开(公告)号：US09639473B1

公开(公告)日：2017-05-02

申请号：US14934252

申请日：2015-11-06

申请人： Parallel Machines Ltd.

发明人： Michael Adda ,  Avner Braverman ,  Lior Amar ,  Dan Aloni ,  Lior Khermosh ,  Gal Zuckerman

IPC分类号： G06F13/00 ,  G06F12/0875 ,  G11C7/10 ,  G06F12/0811 ,  G06F12/1081

CPC分类号： G06F12/0875 ,  G06F12/0811 ,  G06F12/0868 ,  G06F12/0888 ,  G06F12/0893 ,  G06F12/1081 ,  G06F2212/2532 ,  G06F2212/283 ,  G06F2212/452

摘要： Described herein are systems and methods to prevent a controller in a DDIO (data direct input output) system from shifting currently-required data out of a cache memory. In one embodiment, a compute element disables caching of some specific addresses in a non-cache memory, but still enables caching of other addresses in the non-cache memory, thereby practically disabling the DDIO system, so that data sets not currently needed are placed in the addresses in the non-cache memory which are not cached. As a result, currently-required data are not shifted out of cache memory. The compute element then determines that the data sets, which formerly avoided being cached, are now required. The system therefore copies the data sets that are now required from addresses in non-cache memory not accessible to cache memory, to addresses in non-cache memory accessible to cache memory, thereby allowing the caching and processing of such data sets.

公开(公告)号：US09594696B1

公开(公告)日：2017-03-14

申请号：US14740793

申请日：2015-06-16

申请人： Parallel Machines Ltd.

发明人： Avner Braverman ,  Michael Adda ,  Lior Amar ,  Lior Khermosh ,  Eli Finer ,  Gal Zuckerman

IPC分类号： G06F12/00 ,  G06F12/10 ,  G06F13/16

CPC分类号： G06F9/542 ,  G06F8/10 ,  G06F8/451 ,  G06F9/461 ,  G06F9/4843 ,  G06F9/4881 ,  G06F9/5016 ,  G06F9/5066 ,  G06F9/544 ,  G06F11/3624 ,  G06F12/084 ,  G06F12/0846 ,  G06F12/1081 ,  G06F13/1663 ,  G06F2212/2532

摘要： Various systems and methods to generate automatically a procedure operative to distributively process a plurality of data sets stored on a plurality of memory modules. Under the instruction of the automatically generated procedure, compute elements request data sets relevant to a particular task, such data sets are fetched from memory modules by data interfaces which provide such data sets to the requesting compute elements, and the compute elements then process the received data sets until the task is completed. Relevant data sets are fetched and processed asynchronously, which means that the relevant data sets need not be fetched and processed in any particular order.

摘要翻译： 自动产生用于分配地处理存储在多个存储器模块上的多个数据集的程序的各种系统和方法。 在自动生成过程的指导下，计算单元请求与特定任务相关的数据集，通过数据接口从存储器模块中提取这些数据集，数据接口将这些数据集提供给请求的计算单元，然后计算单元处理接收的 数据集，直到任务完成。 相关数据集被异步取出和处理，这意味着相关数据集不需要以任何特定的顺序被提取和处理。

公开(公告)号：US09576638B2

公开(公告)日：2017-02-21

申请号：US14375740

申请日：2013-09-25

申请人： CANON KABUSHIKI KAISHA

发明人： Masanori Ichikawa

IPC分类号： G06F11/30 ,  G11C11/406 ,  G06F12/06

CPC分类号： G11C11/40626 ,  G06F11/3037 ,  G06F11/3058 ,  G06F12/063 ,  G06F2212/2532

摘要： An information processing apparatus according to an aspect of the present invention acquires temperature information for each of a plurality of memories in a wide IO memory device, and when execution of a job is instructed, decides on a memory having a lower temperature as the memory to be used by a functional module that corresponds to a function, based on the memory size to be used by the functional module that corresponds to the function, and on the acquired temperature information for the memories.

摘要翻译： 根据本发明的一个方面的信息处理设备获取宽IO存储器件中的多个存储器中的每一个的温度信息，并且当指示作业执行时，将具有较低温度的存储器作为存储器 由与功能相对应的功能模块使用，基于功能模块对应于功能的存储器大小，以及所获取的用于存储器的温度信息。

公开(公告)号：US09575891B2

公开(公告)日：2017-02-21

申请号：US14307164

申请日：2014-06-17

申请人： Advanced Micro Devices, Inc.

发明人： John R. Riley ,  Russell Schreiber ,  Donald R. Weiss ,  John J. Wuu ,  William A. McGee

IPC分类号： G06F12/00 ,  G06F12/06 ,  G11C5/02

CPC分类号： G06F12/0607 ,  G06F12/0623 ,  G06F2212/1052 ,  G06F2212/2532 ,  G11C5/025

摘要： A system and method for floorplanning a memory. A computing system includes a processing unit which generates memory access requests and a memory. The size of each memory line in the memory includes M bits. The memory includes at least a primary bank and a sidecar bank. The primary bank includes a first portion with (M−A) bits of the M bits of a memory line being accessed. The sidecar bank includes a second portion with A bits of the M bits of the memory line being accessed. The primary bank and the sidecar bank have a same height, which is less than a height that would be used if the primary bank included all M bits in each memory line. The completion of the access request for the M bits of the memory line is done at a similar time, such as a same clock cycle.

摘要翻译： 用于布局规划存储器的系统和方法。 计算系统包括生成存储器访问请求的处理单元和存储器。 存储器中每个存储器线的大小包括M位。 记忆体至少包括一个主要银行和一个侧边银行。 主存储体包括第一部分，存取存储器线的M位的（M-A）位。 旁边组包括存取线的M位的A位的第二部分。 主要银行和旁边银行的高度相同，如果主存储包含每个存储行中的所有M位，则低于要使用的高度。 对于存储器线路的M位的访问请求的完成在类似的时间完成，例如相同的时钟周期。