公开(公告)号：US20090027065A1

公开(公告)日：2009-01-29

申请号：US11781994

申请日：2007-07-24

申请人： Jente B. Kuang ,  Jerry C. Keo ,  Hung C. Ngo ,  Kevin J. Nowka ,  Liang-Teck Pang ,  Jayakumaran Sivagnaname

发明人： Jente B. Kuang ,  Jerry C. Keo ,  Hung C. Ngo ,  Kevin J. Nowka ,  Liang-Teck Pang ,  Jayakumaran Sivagnaname

IPC分类号： G01R27/28

CPC分类号： G11C29/50 ,  G01R31/31937 ,  G11C29/50012 ,  G11C2029/1202 ,  G11C2029/1204

摘要： A wordline-to-bitline timing ring oscillator circuit for evaluating storage cell access time provides data on internal bitline access timing, and in particular the total wordline select-to-bitline read output timing. Columns of a storage array are connected in a ring, forming a ring oscillator. The bitline read circuit output of each column is connected to a wordline select input of a next column, with a net inversion around the ring, so that a ring oscillator is formed. The period of oscillation of the ring oscillator is determined by the total wordline select-to-bitline read circuit output timing for a first phase and the pre-charge interval time for the other phase, with the bitline read timing dominating. The circuit may be applied both to small-signal storage arrays, with the sense amplifier timing included within the ring oscillator period, or to large-signal storage arrays, with the read evaluate circuit timing included.

摘要翻译： 用于评估存储单元访问时间的字线到位线定时环形振荡器电路提供关于内部位线访问定时的数据，特别是总字线选择到位线读出输出定时。 存储阵列的列以环形连接，形成环形振荡器。 每列的位线读取电路输出连接到下一列的字线选择输入，环绕环反转，从而形成环形振荡器。 环形振荡器的振荡周期由第一相的总字线选择到位线读取电路输出定时和另一相的预充电间隔时间决定，而位线读取时序主导。 该电路可以应用于小信号存储阵列，其中包括在环形振荡器周期内的读出放大器定时，或者包括读取评估电路时序的大信号存储阵列。