Mixed-type adder comprising multiple sub-adders having different carry propagation schemes
    1.
    发明授权
    Mixed-type adder comprising multiple sub-adders having different carry propagation schemes 失效
    混合型加法器包括具有不同进位传播方案的多个子加法器

    公开(公告)号:US07562107B2

    公开(公告)日:2009-07-14

    申请号:US11134615

    申请日:2005-05-19

    IPC分类号: G06F7/50

    CPC分类号: G06F7/506 G06F7/507 G06F7/508

    摘要: Disclosed is a mixed-type adder with optimized design costs. The mixed-type adder includes I sub adders, (where, I is a positive number larger than 1). An overall bit width of the mixed-type adder is divided into I bit groups which are respectively allocated to the I sub adders. The I sub adders have different carry propagation schemes and are connected in series through a carry signal.

    摘要翻译: 公开了一种具有优化设计成本的混合型加法器。 混合型加法器包括I子加法器(其中,I为大于1的正数)。 混合型加法器的总位宽度分为分配给I子加法器的I比特组。 I子加法器具有不同的进位传播方案,并通过进位信号串联连接。

    Data transmitting circuit and method based on differential value data encoding
    3.
    发明授权
    Data transmitting circuit and method based on differential value data encoding 失效
    基于差分值数据编码的数据传输电路及方法

    公开(公告)号:US07170431B2

    公开(公告)日:2007-01-30

    申请号:US10967647

    申请日:2004-10-14

    IPC分类号: H03M7/00

    CPC分类号: H03M7/3044 H03M7/18

    摘要: Disclosed is a data transmitting circuit and a method based on a differential value data encoding to reduce a data transmitting time by transmitting an encoded differential value. The circuit comprises an encoder for encoding and outputting a differential value between a currently transmitted data value and a previously transmitted data value, wherein the encoder inverts a phase of one output signal among 2n(namely, N)-output signals in response to n-bit input value and outputs an encoded data value; and a decoder for decoding the output value of the encoder and restoring the original data value, wherein the decoder restores the original data value by adding an output value from the encoder and the previous original data value.

    摘要翻译: 公开了一种数据发送电路和基于差分值数据编码的方法,以通过发送编码的差分值来减少数据发送时间。 该电路包括一个编码器,用于对当前传输的数据值和先前发送的数据值之间的差分值进行编码和输出,其中编码器将两个输出信号的相位反相(即N) - 响应于n位输入值输出信号并输出​​编码数据值; 以及解码器,用于对编码器的输出值进行解码并恢复原始数据值,其中解码器通过将来自编码器的输出值和先前的原始数据值相加来恢复原始数据值。

    Data transmitting circuit and method based on differential value data encoding
    7.
    发明申请
    Data transmitting circuit and method based on differential value data encoding 失效
    基于差分值数据编码的数据传输电路及方法

    公开(公告)号:US20060007026A1

    公开(公告)日:2006-01-12

    申请号:US10967647

    申请日:2004-10-14

    IPC分类号: H03M7/00

    CPC分类号: H03M7/3044 H03M7/18

    摘要: Disclosed is a data transmitting circuit and a method based on a differential value data encoding to reduce a data transmitting time by transmitting an encoded differential value. The circuit comprises an encoder for encoding and outputting a differential value between a currently transmitted data value and a previously transmitted data value, wherein the encoder inverts a phase of one output signal among 2n(namely, N)-output signals in response to n-bit input value and outputs an encoded data value; and a decoder for decoding the output value of the encoder and restoring the original data value, wherein the decoder restores the original data value by adding an output value from the encoder and the previous original data value.

    摘要翻译: 公开了一种数据发送电路和基于差分值数据编码的方法,以通过发送编码的差分值来减少数据发送时间。 该电路包括一个编码器,用于对当前传输的数据值和先前发送的数据值之间的差分值进行编码和输出,其中编码器将两个输出信号的相位反相(即N) - 响应于n位输入值输出信号并输出​​编码数据值; 以及解码器,用于对编码器的输出值进行解码并恢复原始数据值,其中解码器通过将来自编码器的输出值和先前的原始数据值相加来恢复原始数据值。