公开(公告)号：US06190954B1

公开(公告)日：2001-02-20

申请号：US09229381

申请日：1999-01-11

申请人： Jian-Hsing Lee ,  Shui-Hung Chen ,  Jiaw Ren Shih

发明人： Jian-Hsing Lee ,  Shui-Hung Chen ,  Jiaw Ren Shih

IPC分类号： H01L218238

CPC分类号： H01L21/823892 ,  H01L27/0921

摘要： A method is disclosed to provide for more robust latchup-immune CMOS transistors by increasing the breakover voltage VBO, or trigger point, of the parasitic npn and pnp transistors present in CMOS structures. These goals have been achieved by adding a barrier layer to both the n-well and p-well of a twin-well CMOS structure, thus increasing the energy gap for electrons and holes of the parasitic npn and pnp transistor, respectively.

摘要翻译： 公开了一种通过增加存在于CMOS结构中的寄生npn和pnp晶体管的跳转电压VBO或触发点来提供更稳健的闭锁免疫CMOS晶体管的方法。 这些目标已经通过在双井CMOS结构的n阱和p阱两者中添加阻挡层来实现，从而分别增加了寄生npn和pnp晶体管的电子和空穴的能隙。