公开(公告)号：US08492794B2

公开(公告)日：2013-07-23

申请号：US13048366

申请日：2011-03-15

申请人： Jin Cai ,  Kevin K. Chan ,  Wilfried E. Haensch ,  Tak H. Ning

发明人： Jin Cai ,  Kevin K. Chan ,  Wilfried E. Haensch ,  Tak H. Ning

IPC分类号： H01L29/66

CPC分类号： H01L29/737 ,  H01L21/76229 ,  H01L29/0649 ,  H01L29/0821 ,  H01L29/165 ,  H01L29/66242 ,  H01L29/7375

摘要： A vertical heterojunction bipolar transistor (HBT) includes doped polysilicon having a doping of a first conductivity type as a wide-gap-emitter with an energy bandgap of about 1.12 eV and doped single crystalline Ge having a doping of the second conductivity type as the base having the energy bandgap of about 0.66 eV. Doped single crystalline Ge having of doping of the first conductivity type is employed as the collector. Because the base and the collector include the same semiconductor material, i.e., Ge, having the same lattice constant, there is no lattice mismatch issue between the collector and the base. Further, because the emitter is polycrystalline and the base is single crystalline, there is no lattice mismatch issue between the base and the emitter.

公开(公告)号：US08441084B2

公开(公告)日：2013-05-14

申请号：US13048342

申请日：2011-03-15

申请人： Jin Cai ,  Kevin K. Chan ,  Wilfried E. Haensch ,  Tak H. Ning

发明人： Jin Cai ,  Kevin K. Chan ,  Wilfried E. Haensch ,  Tak H. Ning

IPC分类号： H01L29/66 ,  H01L29/04

CPC分类号： H01L29/737 ,  H01L29/0808 ,  H01L29/0821 ,  H01L29/66242 ,  H01L29/66265

摘要： A horizontal heterojunction bipolar transistor (HBT) includes doped single crystalline Ge having a doping of the first conductivity type as the base having an energy bandgap of about 0.66 eV, and doped polysilicon having a doping of a second conductivity type as a wide-gap-emitter having an energy bandgap of about 1.12 eV. In one embodiment, doped polysilicon having a doping of the second conductivity type is employed as the collector. In other embodiments, a single crystalline Ge having a doping of the second conductivity type is employed as the collector. In such embodiments, because the base and the collector include the same semiconductor material, i.e., Ge, having the same lattice constant, there is no lattice mismatch issue between the collector and the base. In both embodiments, because the emitter is polycrystalline and the base is single crystalline, there is no lattice mismatch issue between the base and the emitter.

摘要翻译： 水平异质结双极晶体管（HBT）包括具有第一导电类型的掺杂的掺杂单晶Ge作为具有约0.66eV的能带隙的基极，以及掺杂有第二导电类型的掺杂多晶硅作为宽间隙 - 发射体具有约1.12eV的能带隙。 在一个实施例中，采用具有第二导电类型掺杂的掺杂多晶硅作为集电极。 在其它实施例中，采用具有第二导电类型掺杂的单晶Ge作为集电极。 在这样的实施例中，由于基极和集电极包括具有相同晶格常数的相同的半导体材料即Ge，所以在集电极和基极之间不存在晶格失配问题。 在两个实施例中，由于发射极是多晶的并且基极是单晶的，所以在基极和发射极之间不存在晶格失配问题。

公开(公告)号：US20120235143A1

公开(公告)日：2012-09-20

申请号：US13048366

申请日：2011-03-15

申请人： Jin Cai ,  Kevin K. Chan ,  Wilfried E. Haensch ,  Tak H. Ning

发明人： Jin Cai ,  Kevin K. Chan ,  Wilfried E. Haensch ,  Tak H. Ning

IPC分类号： H01L29/737 ,  H01L21/331

CPC分类号： H01L29/737 ,  H01L21/76229 ,  H01L29/0649 ,  H01L29/0821 ,  H01L29/165 ,  H01L29/66242 ,  H01L29/7375

摘要： A vertical heterojunction bipolar transistor (HBT) includes doped polysilicon having a doping of a first conductivity type as a wide-gap-emitter with an energy bandgap of about 1.12 eV and doped single crystalline Ge having a doping of the second conductivity type as the base having the energy bandgap of about 0.66 eV. Doped single crystalline Ge having of doping of the first conductivity type is employed as the collector. Because the base and the collector include the same semiconductor material, i.e., Ge, having the same lattice constant, there is no lattice mismatch issue between the collector and the base. Further, because the emitter is polycrystalline and the base is single crystalline, there is no lattice mismatch issue between the base and the emitter.

摘要翻译： 垂直异质结双极晶体管（HBT）包括具有掺杂第一导电类型的掺杂多晶硅作为具有约1.12eV的能带隙的宽间隙发射极，并且具有掺杂第二导电类型的掺杂单晶Ge作为基极 具有约0.66eV的能量带隙。 采用具有第一导电类型掺杂的掺杂单晶Ge作为集电体。 因为基极和集电极包括具有相同晶格常数的相同的半导体材料即Ge，所以在集电极和基极之间不存在晶格失配问题。 此外，由于发射极是多晶的并且基极是单晶的，所以在基极和发射极之间不存在晶格失配问题。

公开(公告)号：US08106458B2

公开(公告)日：2012-01-31

申请号：US12348391

申请日：2009-01-05

申请人： Jin Cai ,  Wilfried E. Haensch ,  Tak H. Ning

发明人： Jin Cai ,  Wilfried E. Haensch ,  Tak H. Ning

IPC分类号： H01L27/12

CPC分类号： H01L21/84 ,  H01L27/1203 ,  H01L29/78648

摘要： The present invention relates to methods and devices for reducing the threshold voltage difference between an n-type field effect transistor (n-FET) and a p-type field effect transistor (p-FET) in a complementary metal-oxide-semiconductor (CMOS) circuit located on a silicon-on-insulator (SOI) substrate. Specifically, a substrate bias voltage is applied to the CMOS circuit for differentially adjusting the threshold voltages of the n-FET and the p-FET. For example, a positive substrate bias voltage can be used to reduce the threshold voltage of the n-FET but increase that of the p-FET, while a negative substrate bias voltage can be used to increase the threshold voltage of the n-FET but reduce that of the p-FET. Further, two or more substrate bias voltages of different magnitudes and/or directions can be used for differentially adjusting the n-FET and p-FET threshold voltages in two or more different CMOS circuits or groups of CMOS circuits.

摘要翻译： 本发明涉及用于降低互补金属氧化物半导体（CMOS）中的n型场效应晶体管（n-FET）和p型场效应晶体管（p-FET）之间的阈值电压差的方法和装置 ）电路，其位于绝缘体上硅（SOI）衬底上。 具体地，将衬底偏置电压施加到CMOS电路以差分调节n-FET和p-FET的阈值电压。 例如，可以使用正衬底偏置电压来降低n-FET的阈值电压，但是增加p-FET的阈值电压，而负衬底偏置电压可以用于增加n-FET的阈值电压，但是 减少p-FET的电流。 此外，可以使用不同幅度和/或方向的两个或更多个衬底偏置电压来差分调节两个或更多个不同CMOS电路或CMOS电路组中的n-FET和p-FET阈值电压。

公开(公告)号：US20090108355A1

公开(公告)日：2009-04-30

申请号：US12348391

申请日：2009-01-05

申请人： Jin Cai ,  Wilfried E. Haensch ,  Tak H. Ning

发明人： Jin Cai ,  Wilfried E. Haensch ,  Tak H. Ning

IPC分类号： H01L27/092

CPC分类号： H01L21/84 ,  H01L27/1203 ,  H01L29/78648

摘要： The present invention relates to methods and devices for reducing the threshold voltage difference between an n-type field effect transistor (n-FET) and a p-type field effect transistor (p-FET) in a complementary metal-oxide-semiconductor (CMOS) circuit located on a silicon-on-insulator (SOI) substrate. Specifically, a substrate bias voltage is applied to the CMOS circuit for differentially adjusting the threshold voltages of the n-FET and the p-FET. For example, a positive substrate bias voltage can be used to reduce the threshold voltage of the n-FET but increase that of the p-FET, while a negative substrate bias voltage can be used to increase the threshold voltage of the n-FET but reduce that of the p-FET. Further, two or more substrate bias voltages of different magnitudes and/or directions can be used for differentially adjusting the n-FET and p-FET threshold voltages in two or more different CMOS circuits or groups of CMOS circuits.

摘要翻译： 本发明涉及用于降低互补金属氧化物半导体（CMOS）中的n型场效应晶体管（n-FET）和p型场效应晶体管（p-FET）之间的阈值电压差的方法和装置 ）电路，其位于绝缘体上硅（SOI）衬底上。 具体地，将衬底偏置电压施加到CMOS电路以差分调节n-FET和p-FET的阈值电压。 例如，可以使用正衬底偏置电压来降低n-FET的阈值电压，但是增加p-FET的阈值电压，而负衬底偏置电压可以用于增加n-FET的阈值电压，但是 减少p-FET的电流。 此外，可以使用不同幅度和/或方向的两个或更多个衬底偏置电压来差分调节两个或更多个不同CMOS电路或CMOS电路组中的n-FET和p-FET阈值电压。

公开(公告)号：US20120313216A1

公开(公告)日：2012-12-13

申请号：US13158419

申请日：2011-06-12

申请人： Jin Cai ,  Robert H. Dennard ,  Wilfried E. Haensch ,  Tak H. Ning

发明人： Jin Cai ,  Robert H. Dennard ,  Wilfried E. Haensch ,  Tak H. Ning

IPC分类号： H01L27/082 ,  H01L21/8228

CPC分类号： H01L27/1203 ,  H01L21/8228 ,  H01L21/84 ,  H01L27/082

摘要： An example embodiment is a complementary transistor inverter circuit. The circuit includes a semiconductor-on-insulator (SOI) substrate, a lateral PNP bipolar transistor fabricated on the SOI substrate, and a lateral NPN bipolar transistor fabricated on the SOI substrate. The lateral PNP bipolar transistor includes a PNP base, a PNP emitter, and a PNP collector. The lateral NPN bipolar transistor includes a NPN base, a NPN emitter, and a NPN collector. The PNP base, the PNP emitter, the PNP collector, the NPN base, the NPN emitter, and the NPN collector abut the buried insulator of the SOI substrate.

摘要翻译： 示例性实施例是互补晶体管反相器电路。 电路包括绝缘体上半导体（SOI）衬底，制造在SOI衬底上的横向PNP双极晶体管，以及制造在SOI衬底上的横向NPN双极晶体管。 横向PNP双极晶体管包括PNP基极，PNP发射极和PNP集电极。 横向NPN双极晶体管包括NPN基极，NPN发射极和NPN集电极。 PNP基极，PNP发射极，PNP集电极，NPN基极，NPN发射极和NPN集电极邻接SOI衬底的埋层绝缘体。

公开(公告)号：US20120112285A1

公开(公告)日：2012-05-10

申请号：US13344006

申请日：2012-01-05

申请人： Jin Cai ,  Wilfried E. Haensch ,  Tak H. Ning

发明人： Jin Cai ,  Wilfried E. Haensch ,  Tak H. Ning

IPC分类号： H01L27/12

CPC分类号： H01L21/84 ,  H01L27/1203 ,  H01L29/78648

摘要： The present invention relates to methods and devices for reducing the threshold voltage difference between an n-type field effect transistor (n-FET) and a p-type field effect transistor (p-FET) in a complementary metal-oxide-semiconductor (CMOS) circuit located on a silicon-on-insulator (SOI) substrate. Specifically, a substrate bias voltage is applied to the CMOS circuit for differentially adjusting the threshold voltages of the n-FET and the p-FET. For example, a positive substrate bias voltage can be used to reduce the threshold voltage of the n-FET but increase that of the p-FET, while a negative substrate bias voltage can be used to increase the threshold voltage of the n-FET but reduce that of the p-FET. Further, two or more substrate bias voltages of different magnitudes and/or directions can be used for differentially adjusting the n-FET and p-FET threshold voltages in two or more different CMOS circuits or groups of CMOS circuits.

摘要翻译： 本发明涉及用于降低互补金属氧化物半导体（CMOS）中的n型场效应晶体管（n-FET）和p型场效应晶体管（p-FET）之间的阈值电压差的方法和装置 ）电路，其位于绝缘体上硅（SOI）衬底上。 具体地，将衬底偏置电压施加到CMOS电路以差分调节n-FET和p-FET的阈值电压。 例如，可以使用正衬底偏置电压来降低n-FET的阈值电压，但是增加p-FET的阈值电压，而负衬底偏置电压可以用于增加n-FET的阈值电压，但是 减少p-FET的电流。 此外，可以使用不同幅度和/或方向的两个或更多个衬底偏置电压来差分调节两个或更多个不同CMOS电路或CMOS电路组中的n-FET和p-FET阈值电压。

公开(公告)号：US07479418B2

公开(公告)日：2009-01-20

申请号：US11329643

申请日：2006-01-11

申请人： Jin Cai ,  Wilfried E. Haensch ,  Tak H. Ning

发明人： Jin Cai ,  Wilfried E. Haensch ,  Tak H. Ning

IPC分类号： H01L21/00

CPC分类号： H01L21/84 ,  H01L27/1203 ,  H01L29/78648

摘要： The present invention relates to methods for reducing the threshold voltage difference between an n-type field effect transistor (n-FET) and a p-type field effect transistor (p-FET) in a complementary metal-oxide-semiconductor (CMOS) circuit located on a silicon-on-insulator (SOI) substrate. Specifically, a substrate bias voltage is applied to the CMOS circuit for differentially adjusting the threshold voltages of the n-FET and the p-FET. For example, a positive substrate bias voltage can be used to reduce the threshold voltage of the n-FET but increase that of the p-FET, while a negative substrate bias voltage can be used to increase the threshold voltage of the n-FET but reduce that of the p-FET. Further, two or more substrate bias voltages of different magnitudes and/or directions can be used for differentially adjusting the n-FET and p-FET threshold voltages in two or more different CMOS circuits or groups of CMOS circuits.

摘要翻译： 本发明涉及用于降低互补金属氧化物半导体（CMOS）电路中的n型场效应晶体管（n-FET）和p型场效应晶体管（p-FET）之间的阈值电压差的方法 位于绝缘体上硅（SOI）衬底上。 具体地，将衬底偏置电压施加到CMOS电路以差分调节n-FET和p-FET的阈值电压。 例如，可以使用正衬底偏置电压来降低n-FET的阈值电压，但是增加p-FET的阈值电压，而负衬底偏置电压可以用于增加n-FET的阈值电压，但是 减少p-FET的电流。 此外，可以使用不同幅度和/或方向的两个或更多个衬底偏置电压来差分调节两个或更多个不同CMOS电路或CMOS电路组中的n-FET和p-FET阈值电压。

公开(公告)号：US08531001B2

公开(公告)日：2013-09-10

申请号：US13158419

申请日：2011-06-12

申请人： Jin Cai ,  Robert H. Dennard ,  Wilfried E. Haensch ,  Tak H. Ning

发明人： Jin Cai ,  Robert H. Dennard ,  Wilfried E. Haensch ,  Tak H. Ning

IPC分类号： H01L21/70

CPC分类号： H01L27/1203 ,  H01L21/8228 ,  H01L21/84 ,  H01L27/082

摘要： An example embodiment is a complementary transistor inverter circuit. The circuit includes a semiconductor-on-insulator (SOI) substrate, a lateral PNP bipolar transistor fabricated on the SOI substrate, and a lateral NPN bipolar transistor fabricated on the SOI substrate. The lateral PNP bipolar transistor includes a PNP base, a PNP emitter, and a PNP collector. The lateral NPN bipolar transistor includes a NPN base, a NPN emitter, and a NPN collector. The PNP base, the PNP emitter, the PNP collector, the NPN base, the NPN emitter, and the NPN collector abut the buried insulator of the SOI substrate.

摘要翻译： 示例性实施例是互补晶体管反相器电路。 电路包括绝缘体上半导体（SOI）衬底，制造在SOI衬底上的横向PNP双极晶体管，以及制造在SOI衬底上的横向NPN双极晶体管。 横向PNP双极晶体管包括PNP基极，PNP发射极和PNP集电极。 横向NPN双极晶体管包括NPN基极，NPN发射极和NPN集电极。 PNP基极，PNP发射极，PNP集电极，NPN基极，NPN发射极和NPN集电极邻接SOI衬底的埋层绝缘体。

公开(公告)号：US08415744B2

公开(公告)日：2013-04-09

申请号：US13344006

申请日：2012-01-05

申请人： Jin Cai ,  Wilfried E. Haensch ,  Tak H. Ning

发明人： Jin Cai ,  Wilfried E. Haensch ,  Tak H. Ning

IPC分类号： H01L27/12

CPC分类号： H01L21/84 ,  H01L27/1203 ,  H01L29/78648

摘要： The present invention relates to methods and devices for reducing the threshold voltage difference between an n-type field effect transistor (n-FET) and a p-type field effect transistor (p-FET) in a complementary metal-oxide-semiconductor (CMOS) circuit located on a silicon-on-insulator (SOI) substrate. Specifically, a substrate bias voltage is applied to the CMOS circuit for differentially adjusting the threshold voltages of the n-FET and the p-FET. For example, a positive substrate bias voltage can be used to reduce the threshold voltage of the n-FET but increase that of the p-FET, while a negative substrate bias voltage can be used to increase the threshold voltage of the n-FET but reduce that of the p-FET. Further, two or more substrate bias voltages of different magnitudes and/or directions can be used for differentially adjusting the n-FET and p-FET threshold voltages in two or more different CMOS circuits or groups of CMOS circuits.

摘要翻译： 本发明涉及用于降低互补金属氧化物半导体（CMOS）中的n型场效应晶体管（n-FET）和p型场效应晶体管（p-FET）之间的阈值电压差的方法和装置 ）电路，其位于绝缘体上硅（SOI）衬底上。 具体地，将衬底偏置电压施加到CMOS电路以差分调节n-FET和p-FET的阈值电压。 例如，可以使用正的衬底偏置电压来降低n-FET的阈值电压，但是增加p-FET的阈值电压，而负的衬底偏置电压可以用于增加n-FET的阈值电压，但是 减少p-FET的电流。 此外，可以使用不同幅度和/或方向的两个或更多个衬底偏置电压来差分调节两个或更多个不同CMOS电路或CMOS电路组中的n-FET和p-FET阈值电压。