公开(公告)号：US08536888B2

公开(公告)日：2013-09-17

申请号：US12981618

申请日：2010-12-30

申请人： Jinn-Yeh Chien ,  Hao-Jie Zhan

发明人： Jinn-Yeh Chien ,  Hao-Jie Zhan

IPC分类号： G01R31/3187

CPC分类号： G01R31/31716

摘要： An integrated circuit (IC), comprises a receiver on an IC substrate. The receiver is configured to receive a stressed input signal. A built in self test (BIST) circuit is provided on the IC substrate for testing the receiver. The BIST circuit comprises an encoder configured for receiving an input signal and identifying whether a first condition is present, in which two or more consecutive input data bits have the same polarity as each other. An output driver circuit provides the stressed input signal corresponding to the two or more consecutive input data bits. The stressed input signal has an amplitude that is larger when the encoder identifies that the first condition is present and smaller when the encoder identifies that two or more consecutive input data bits have different polarity from each other.

摘要翻译： 集成电路（IC），包括IC基板上的接收器。 接收器被配置为接收受压输入信号。 在IC基板上提供内置自检（BIST）电路，用于测试接收器。 BIST电路包括编码器，其被配置为接收输入信号并且识别是否存在第一条件，其中两个或更多个连续的输入数据位具有彼此相同的极性。 输出驱动器电路提供对应于两个或更多个连续输入数据位的应力输入信号。 当编码器识别出两个或多个连续的输入数据位彼此具有不同的极性时，编码器识别出第一个条件存在时，应力输入信号具有较大的幅度。

公开(公告)号：US20120169361A1

公开(公告)日：2012-07-05

申请号：US12981618

申请日：2010-12-30

申请人： Jinn-Yeh CHIEN ,  Hao-Jie Zhan

发明人： Jinn-Yeh CHIEN ,  Hao-Jie Zhan

IPC分类号： G01R31/3187

CPC分类号： G01R31/31716

摘要： An integrated circuit (IC), comprises a receiver on an IC substrate. The receiver is configured to receive a stressed input signal. A built in self test (BIST) circuit is provided on the IC substrate for testing the receiver. The BIST circuit comprises an encoder configured for receiving an input signal and identifying whether a first condition is present, in which two or more consecutive input data bits have the same polarity as each other. An output driver circuit provides the stressed input signal corresponding to the two or more consecutive input data bits. The stressed input signal has an amplitude that is larger when the encoder identifies that the first condition is present and smaller when the encoder identifies that two or more consecutive input data bits have different polarity from each other.

摘要翻译： 集成电路（IC），包括IC基板上的接收器。 接收器被配置为接收受压输入信号。 在IC基板上提供内置自检（BIST）电路，用于测试接收器。 BIST电路包括编码器，其被配置为接收输入信号并且识别是否存在第一条件，其中两个或更多个连续的输入数据位具有彼此相同的极性。 输出驱动器电路提供对应于两个或更多个连续输入数据位的应力输入信号。 当编码器识别出两个或多个连续的输入数据位彼此具有不同的极性时，编码器识别出第一个条件存在时，应力输入信号具有较大的幅度。

公开(公告)号：US08824987B2

公开(公告)日：2014-09-02

申请号：US13191512

申请日：2011-07-27

申请人： Hao-Jie Zhan

发明人： Hao-Jie Zhan

IPC分类号： H04B1/10 ,  H03G3/34

CPC分类号： H03G3/344

摘要： A squelch detector includes a first circuit, a second circuit, and a comparator. The first circuit is configured to receive a first pair of differential input signals and in response output a second pair of differential signals. The second pair of differential signals have higher voltages than the first pair of differential input signals. The second circuit is coupled to the first circuit and is configured to extract first and second voltage levels from the second pair of differential signals. The comparator is configured to output a squelch level signal based on a comparison of the first voltage level and a third voltage level. The third voltage level is based on the second voltage level and a reference voltage.

摘要翻译： 静噪检测器包括第一电路，第二电路和比较器。 第一电路被配置为接收第一对差分输入信号，并且响应于输出第二对差分信号。 第二对差分信号具有比第一对差分输入信号更高的电压。 第二电路耦合到第一电路并且被配置为从第二对差分信号中提取第一和第二电压电平。 比较器被配置为基于第一电压电平和第三电压电平的比较来输出静噪电平信号。 第三电压电平基于第二电压电平和参考电压。

公开(公告)号：US09287856B2

公开(公告)日：2016-03-15

申请号：US13302404

申请日：2011-11-22

申请人： Hao-Jie Zhan ,  Tsung-Hsin Yu

发明人： Hao-Jie Zhan ,  Tsung-Hsin Yu

IPC分类号： B23K11/24 ,  H03K3/356 ,  H03K19/0185

CPC分类号： G06F13/4282 ,  G05F3/26 ,  G06F1/3296 ,  H03K3/356104 ,  H03K19/018521

摘要： A circuit includes a switching circuit, a node, and a tracking circuit. The switching circuit has a first terminal, a second terminal, and a third terminal. The node has a node voltage. The tracking circuit is electrically coupled to the third terminal and the node, and configured to receive the node voltage and generate a control voltage at the third terminal based on the node voltage.

摘要翻译： 电路包括开关电路，节点和跟踪电路。 开关电路具有第一端子，第二端子和第三端子。 节点具有节点电压。 跟踪电路电耦合到第三终端和节点，并且被配置为接收节点电压并且基于节点电压在第三终端产生控制电压。

公开(公告)号：US08873213B2

公开(公告)日：2014-10-28

申请号：US13420072

申请日：2012-03-14

申请人： Hao-Jie Zhan ,  Tsung-Hsin Yu

发明人： Hao-Jie Zhan ,  Tsung-Hsin Yu

IPC分类号： H02H3/22 ,  H03K5/08

CPC分类号： H03K3/356113

摘要： A voltage swing decomposition circuit includes first and second clamp circuits and a protection circuit. The first clamp circuit is configured to clamp an output node of the first clamp circuit at a first voltage level when an input node of the voltage swing decomposition circuit has a voltage higher than the first voltage level. The second clamp circuit is configured to clamp an output node of the second clamp circuit at a second voltage level, higher than the first level, when the voltage of the input node is lower than the second voltage level. The protection circuit is coupled to the output nodes of the first and second clamp circuits, and is configured to selectively set an output node of the protection circuit to the first or second voltage level. The first and second clamp circuits are coupled together by the output node of the protection circuit.

摘要翻译： 电压摆动分解电路包括第一和第二钳位电路和保护电路。 第一钳位电路被配置为当电压摆幅分解电路的输入节点具有高于第一电压电平的电压时，将第一钳位电路的输出节点钳位在第一电压电平。 当输入节点的电压低于第二电压电平时，第二钳位电路被配置为将第二钳位电路的输出节点钳位在高于第一电平的第二电压电平。 保护电路耦合到第一和第二钳位电路的输出节点，并且被配置为选择性地将保护电路的输出节点设置为第一或第二电压电平。 第一和第二钳位电路由保护电路的输出节点耦合在一起。