公开(公告)号：US20070198772A1

公开(公告)日：2007-08-23

申请号：US10589398

申请日：2004-05-26

申请人： Jinquan Dai ,  Luddy Harrison ,  Long Li ,  Bo Huang

发明人： Jinquan Dai ,  Luddy Harrison ,  Long Li ,  Bo Huang

IPC分类号： G06F12/00

CPC分类号： G06F12/0842 ,  G06F8/4442 ,  G06F12/0893

摘要： Automatic software controlled caching generations in network applications are described herein. In one embodiment, a candidate representing a plurality of instructions of a plurality of threads that perform one or more external memory accesses is identified, where the external memory accesses have a substantially identical base address. One or more directives and/or instructions are inserted into an instruction stream corresponding to the identified candidate to maintain contents of at least one of a content addressable memory (CAM) and local memory (LM) of a processor, and to modify at least one of the external memory access to access at least one of the CAM and LM of the processor without having to perform the respective external memory access. Other methods and apparatuses are also described.

摘要翻译： 本文描述了网络应用中自动软件控制的缓存世代。 在一个实施例中，识别表示执行一个或多个外部存储器访问的多个线程的多个指令的候选者，其中外部存储器访问具有基本上相同的基地址。 将一个或多个指令和/或指令插入与所识别的候选对应的指令流中，以维持处理器的内容可寻址存储器（CAM）和本地存储器（LM）中的至少一个的内容，并修改至少一个 的外部存储器访问以访问处理器的CAM和LM中的至少一个，而不必执行相应的外部存储器访问。 还描述了其它方法和装置。

公开(公告)号：US20050108696A1

公开(公告)日：2005-05-19

申请号：US10714465

申请日：2003-11-14

申请人： Jinquan Dai ,  Luddy Harrison ,  Bo Huang ,  Cotton Seed ,  Long Li

发明人： Jinquan Dai ,  Luddy Harrison ,  Bo Huang ,  Cotton Seed ,  Long Li

IPC分类号： G06F9/45

CPC分类号： G06F8/456

摘要： In some embodiments, a method and apparatus for automatically parallelizing a sequential network application through pipeline transformation are described. In one embodiment, the method includes the configuration of a network processor into a D-stage processor pipeline. Once configured, a sequential network application program is transformed into D-pipeline stages. Once transformed, the D-pipeline stages are executed in parallel within the D-stage processor pipeline. In one embodiment, transformation of a sequential application program is performed by modeling the sequential network program as a flow network model and selecting from the flow network model into a plurality of preliminary pipeline stages. Other embodiments are described and claimed.

摘要翻译： 在一些实施例中，描述了通过流水线变换自动并行化顺序网络应用的方法和装置。 在一个实施例中，该方法包括将网络处理器配置到D级处理器流水线中。 一旦配置，顺序网络应用程序被转换成D流水线阶段。 一旦变换，D级流水线级在D级处理器管线中并行执行。 在一个实施例中，顺序应用程序的转换通过将顺序网络程序建模为流网络模型并从流网络模型选择为多个初级流水线级来执行。 描述和要求保护其他实施例。

公开(公告)号：US08438552B2

公开(公告)日：2013-05-07

申请号：US12751929

申请日：2010-03-31

申请人： Jinquan Dai ,  Luddy Harrison ,  Bo Huang ,  Cotton Seed ,  Long Li

发明人： Jinquan Dai ,  Luddy Harrison ,  Bo Huang ,  Cotton Seed ,  Long Li

IPC分类号： G06F9/45

CPC分类号： G06F8/456

摘要： In some embodiments, a method and apparatus for automatically parallelizing a sequential network application through pipeline transformation are described. In one embodiment, the method includes the configuration of a network processor into a D-stage processor pipeline. Once configured, a sequential network application program is transformed into D-pipeline stages. Once transformed, the D-pipeline stages are executed in parallel within the D-stage processor pipeline. In one embodiment, transformation of a sequential application program is performed by modeling the sequential network program as a flow network model and selecting from the flow network model into a plurality of preliminary pipeline stages. Other embodiments are described and claimed.

摘要翻译： 在一些实施例中，描述了通过流水线变换自动并行化顺序网络应用的方法和装置。 在一个实施例中，该方法包括将网络处理器配置到D级处理器流水线中。 一旦配置，顺序网络应用程序被转换成D流水线阶段。 一旦变换，D级流水线级在D级处理器管线中并行执行。 在一个实施例中，顺序应用程序的转换通过将顺序网络程序建模为流网络模型并从流网络模型选择为多个初级流水线级来执行。 描述和要求保护其他实施例。

公开(公告)号：US20050108499A1

公开(公告)日：2005-05-19

申请号：US10718283

申请日：2003-11-19

申请人： Bo Huang ,  Long Li ,  Jinquan Dai ,  Luddy Harrison

发明人： Bo Huang ,  Long Li ,  Jinquan Dai ,  Luddy Harrison

IPC分类号： G06F12/00

CPC分类号： G06F8/41

摘要： A compilation method includes converting memory access instructions that read or write less than a minimum data access unit (MDAU) to memory access instructions that read or write a multiple of the minimum data access unit, converting the memory access instructions into a format including a base address plus an offset, grouping subsets of the converted memory access instructions into partitions, and vectorizing the converted memory access instructions in the subsets that match instruction patterns.

摘要翻译： 编译方法包括将读取或写入小于最小数据存取单元（MDAU）的存储器访问指令转换成读或写最小数据访问单元的倍数的存储器访问指令，将存储器访问指令转换成包括基底 地址加偏移，将转换的存储器访问指令的子集分组成分区，以及对与指令模式匹配的子集中的转换的存储器访问指令进行向量化。

公开(公告)号：US07793276B2

公开(公告)日：2010-09-07

申请号：US10714465

申请日：2003-11-14

申请人： Jinquan Dai ,  Luddy Harrison ,  Bo Huang ,  Cotton Seed ,  Long Li

发明人： Jinquan Dai ,  Luddy Harrison ,  Bo Huang ,  Cotton Seed ,  Long Li

IPC分类号： G06F9/44 ,  G06F9/45 ,  G06F9/30 ,  G06F7/38 ,  G06F12/00

CPC分类号： G06F8/456

摘要： In some embodiments, a method and apparatus for automatically parallelizing a sequential network application through pipeline transformation are described. In one embodiment, the method includes the configuration of a network processor into a D-stage processor pipeline. Once configured, a sequential network application program is transformed into D-pipeline stages. Once transformed, the D-pipeline stages are executed in parallel within the D-stage processor pipeline. In one embodiment, transformation of a sequential application program is performed by modeling the sequential network program as a flow network model and selecting from the flow network model into a plurality of preliminary pipeline stages. Other embodiments are described and claimed.

摘要翻译： 在一些实施例中，描述了通过流水线变换自动并行化顺序网络应用的方法和装置。 在一个实施例中，该方法包括将网络处理器配置到D级处理器流水线中。 一旦配置，顺序网络应用程序被转换成D流水线阶段。 一旦变换，D级流水线级在D级处理器管线中并行执行。 在一个实施例中，顺序应用程序的转换通过将顺序网络程序建模为流网络模型并从流网络模型选择为多个初级流水线级来执行。 描述和要求保护其他实施例。

公开(公告)号：US20100223605A1

公开(公告)日：2010-09-02

申请号：US12751929

申请日：2010-03-31

申请人： Jinquan Dai ,  Luddy Harrison ,  Bo Huang ,  Cotton Seed ,  Long Li

发明人： Jinquan Dai ,  Luddy Harrison ,  Bo Huang ,  Cotton Seed ,  Long Li

IPC分类号： G06F9/38 ,  G06F9/44 ,  G06F15/16

CPC分类号： G06F8/456

摘要： In some embodiments, a method and apparatus for automatically parallelizing a sequential network application through pipeline transformation are described. In one embodiment, the method includes the configuration of a network processor into a D-stage processor pipeline. Once configured, a sequential network application program is transformed into D-pipeline stages. Once transformed, the D-pipeline stages are executed in parallel within the D-stage processor pipeline. In one embodiment, transformation of a sequential application program is performed by modeling the sequential network program as a flow network model and selecting from the flow network model into a plurality of preliminary pipeline stages. Other embodiments are described and claimed.

摘要翻译： 在一些实施例中，描述了通过流水线变换自动并行化顺序网络应用的方法和装置。 在一个实施例中，该方法包括将网络处理器配置到D级处理器流水线中。 一旦配置，顺序网络应用程序被转换成D流水线阶段。 一旦变换，D级流水线级在D级处理器管线中并行执行。 在一个实施例中，顺序应用程序的转换通过将顺序网络程序建模为流网络模型并从流网络模型选择为多个初级流水线级来执行。 描述和要求保护其他实施例。

公开(公告)号：US20050108695A1

公开(公告)日：2005-05-19

申请号：US10714198

申请日：2003-11-14

申请人： Long Li ,  Cotton Seed ,  Bo Huang ,  Luddy Harrison ,  Jinquan Dai

发明人： Long Li ,  Cotton Seed ,  Bo Huang ,  Luddy Harrison ,  Jinquan Dai

IPC分类号： G06F9/45 ,  G06F9/48

CPC分类号： G06F8/456 ,  G06F9/4843

摘要： In some embodiments, a method and apparatus for an automatic thread-partition compiler are described. In one embodiment, the method includes the transformation of a sequential application program into a plurality of application program threads. Once partitioned, the plurality of application program threads are concurrently executed as respective threads of a multi-threaded architecture. Hence, a performance improvement of the parallel multi-threaded architecture is achieved by hiding memory access latency through or by overlapping memory access with computations or with other memory accesses. Other embodiments are described and claimed.

摘要翻译： 在一些实施例中，描述了用于自动线程分区编译器的方法和装置。 在一个实施例中，该方法包括将顺序应用程序转换为多个应用程序线程。 一旦分区，多个应用程序线程被并行地执行为多线程架构的相应线程。 因此，通过使用计算或与其他存储器访问重叠存储器访问或通过重叠存储器访问来隐藏存储器访问延迟来实现并行多线程架构的性能改进。 描述和要求保护其他实施例。

公开(公告)号：US07606974B2

公开(公告)日：2009-10-20

申请号：US10589398

申请日：2004-05-26

申请人： Jinquan Dai ,  Luddy Harrison ,  Long Li ,  Bo Huang

发明人： Jinquan Dai ,  Luddy Harrison ,  Long Li ,  Bo Huang

IPC分类号： G06F12/02

CPC分类号： G06F12/0842 ,  G06F8/4442 ,  G06F12/0893

摘要： Automatic software controlled caching generations in network applications are described herein. In one embodiment, a candidate representing a plurality of instructions of a plurality of threads that perform one or more external memory accesses is identified, where the external memory accesses have a substantially identical base address. One or more directives and/or instructions are inserted into an instruction stream corresponding to the identified candidate to maintain contents of at least one of a content addressable memory (CAM) and local memory (LM) of a processor, and to modify at least one of the external memory access to access at least one of the CAM and LM of the processor without having to perform the respective external memory access. Other methods and apparatuses are also described.

摘要翻译： 本文描述了网络应用中自动软件控制的缓存世代。 在一个实施例中，识别表示执行一个或多个外部存储器访问的多个线程的多个指令的候选者，其中外部存储器访问具有基本上相同的基地址。 将一个或多个指令和/或指令插入与所识别的候选对应的指令流中，以维持处理器的内容可寻址存储器（CAM）和本地存储器（LM）中的至少一个的内容，并修改至少一个 的外部存储器访问以访问处理器的CAM和LM中的至少一个，而不必执行相应的外部存储器访问。 还描述了其它方法和装置。

公开(公告)号：US07124271B2

公开(公告)日：2006-10-17

申请号：US10684770

申请日：2003-10-14

申请人： Long Li ,  Bo Huang ,  Jinguan Dai ,  Luddy Harrison

发明人： Long Li ,  Bo Huang ,  Jinguan Dai ,  Luddy Harrison

IPC分类号： G06F12/00

CPC分类号： G06F8/441

摘要： A compiler includes a location-assigning module to optimally allocate register locations in various memory blocks of a memory during compilation of a program code in accordance with code proximity of the program code in accessing the register locations and size of each of the memory blocks.

摘要翻译： 编译器包括位置分配模块，用于根据在访问每个存储器块的寄存器位置和大小时程序代码的接近程序在编程程序代码期间最佳地分配存储器的各种存储器块中的寄存器位置。

公开(公告)号：US20050102658A1

公开(公告)日：2005-05-12

申请号：US10684770

申请日：2003-10-14

申请人： Long Li ,  Bo Huang ,  Jinguan Dai ,  Luddy Harrison

发明人： Long Li ,  Bo Huang ,  Jinguan Dai ,  Luddy Harrison

IPC分类号： G06F9/45

CPC分类号： G06F8/441

摘要： A compiler includes a location-assigning module to optimally allocate register locations in various memory blocks of a memory during compilation of a program code in accordance with code proximity of the program code in accessing the register locations and size of each of the memory blocks.

摘要翻译： 编译器包括位置分配模块，用于根据在访问每个存储器块的寄存器位置和大小时程序代码的接近程序在编程程序代码期间最佳地分配存储器的各种存储器块中的寄存器位置。