公开(公告)号：US20120223735A1

公开(公告)日：2012-09-06

申请号：US13038236

申请日：2011-03-01

Applicant: Chirag GULATI ,  Jitendra DASANI ,  Rita ZAPPA ,  Stefano CORBANI

Inventor： Chirag GULATI ,  Jitendra DASANI ,  Rita ZAPPA ,  Stefano CORBANI

IPC: H03K19/003

CPC classification number: H03K19/007

Abstract: A circuit for detecting a single bit upset in a dynamic logic circuit includes a latch circuit having an input for receiving a reset signal, and an output for providing a flag output signal, the latch circuit being clocked by a first clock signal, a first transistor having a drain coupled to the output of the latch circuit, a gate for receiving a second clock signal, and a source, and a second transistor having a drain coupled to the source of the first transistor, a gate for receiving a third clock signal, and a source coupled to ground.

Abstract translation: 一种用于检测动态逻辑电路中的单位置位的电路包括具有用于接收复位信号的输入端的锁存电路和用于提供标志输出信号的输出，所述锁存电路由第一时钟信号计时，第一晶体管 具有耦合到锁存电路的输出的漏极，用于接收第二时钟信号的栅极和源极以及耦合到第一晶体管的源极的漏极的第二晶体管，用于接收第三时钟信号的栅极， 以及耦合到地面的源。

公开(公告)号：US20120163063A1

公开(公告)日：2012-06-28

申请号：US13168609

申请日：2011-06-24

Applicant: Jitendra DASANI

Inventor： Jitendra DASANI

IPC: G11C17/08 ,  H01L21/8246

CPC classification number: G11C17/08 ,  G11C7/065 ,  G11C17/12 ,  H01L27/11226

Abstract: A complementary read-only memory (ROM) cell includes a transistor; and a bit line and a complementary bit line adjacent to the transistor; wherein a drain terminal of the transistor is connected to one of the bit line and the complementary bit line based on data programmed in the ROM cell.

Abstract translation: 互补型只读存储器（ROM）单元包括晶体管; 以及与晶体管相邻的位线和互补位线; 其中所述晶体管的漏极端子基于所述ROM单元中编程的数据连接到所述位线和所述互补位线之一。