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公开(公告)号：US20090189702A1
公开(公告)日：2009-07-30
申请号：US12361259
申请日：2009-01-28
IPC分类号： H03K3/03
CPC分类号： G01R19/16552
摘要： A circuit arrangement for detecting voltage changes, comprising supply terminals configured to apply a first potential and a second potential, a first oscillator and a second oscillator, which are operated with the first potential and the second potential, a voltage dependence of the frequency of the first oscillator differing from a voltage dependence of the frequency of the second oscillator, a first evaluation circuit configured to evaluate the frequency of the first oscillator and a second evaluation circuit configured to evaluate the frequency of the second oscillator, and a comparison circuit configured to compare a value based on the evaluated frequencies of the first oscillator and of the second oscillator with a predetermined threshold value, and to output a voltage change signal indicating an impermissible voltage change between the first potential and the second potential depending on the result of the comparison.
摘要翻译： 一种用于检测电压变化的电路装置，包括被配置为施加第一电位和第二电位的电源端子，第一振荡器和第二振荡器，其以第一电位和第二电位运行，电压依赖性 第一振荡器与第二振荡器的频率的电压依赖性不同，第一评估电路，被配置为评估第一振荡器的频率，以及第二评估电路，被配置为评估第二振荡器的频率;以及比较电路，被配置为比较 基于第一振荡器和具有预定阈值的第二振荡器的估计频率的值，并且根据比较结果输出指示第一电位和第二电位之间的不允许电压变化的电压变化信号。
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公开(公告)号：US07859421B2
公开(公告)日：2010-12-28
申请号：US12361259
申请日：2009-01-28
CPC分类号： G01R19/16552
摘要： A circuit arrangement for detecting voltage changes, comprising supply terminals configured to apply a first potential and a second potential, a first oscillator and a second oscillator, which are operated with the first potential and the second potential, a voltage dependence of the frequency of the first oscillator differing from a voltage dependence of the frequency of the second oscillator, a first evaluation circuit configured to evaluate the frequency of the first oscillator and a second evaluation circuit configured to evaluate the frequency of the second oscillator, and a comparison circuit configured to compare a value based on the evaluated frequencies of the first oscillator and of the second oscillator with a predetermined threshold value, and to output a voltage change signal indicating an impermissible voltage change between the first potential and the second potential depending on the result of the comparison.
摘要翻译： 一种用于检测电压变化的电路装置，包括被配置为施加第一电位和第二电位的电源端子，第一振荡器和第二振荡器，其以第一电位和第二电位运行，电压依赖性 第一振荡器与第二振荡器的频率的电压依赖性不同，被配置为评估第一振荡器的频率的第一评估电路和被配置为评估第二振荡器的频率的第二评估电路，以及配置为比较第二振荡器的比较电路 基于第一振荡器和具有预定阈值的第二振荡器的估计频率的值，并且根据比较结果输出表示第一电位和第二电位之间的不允许电压变化的电压变化信号。
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公开(公告)号：US07830170B2
公开(公告)日：2010-11-09
申请号：US12346240
申请日：2008-12-30
申请人： Thomas Kuenemund , Artur Wroblewski
发明人： Thomas Kuenemund , Artur Wroblewski
IPC分类号： H03K19/096
CPC分类号： H03K19/094 , H03K19/20
摘要： A logic gate comprises a first switch, a second switch, a data network and a keeping circuitry. The first switch is adapted to connect a logic node to a first potential responsive to a transition of an enabling signal. The second switch is adapted to connect the logic node to a second potential via an electrical path responsive to a transition of the enabling signal. The data network is serially connected within the electrical path. The keeping circuitry comprises third and fourth switches serially connected between the logic node and the first potential and being controllable separately from each other, the third switch being adapted to be closed in case a potential on the logic node assumes the first potential and to be opened in case the potential on the logic node assumes the second potential.
摘要翻译： 逻辑门包括第一开关，第二开关，数据网络和保持电路。 第一开关适于将逻辑节点连接到响应于使能信号的转换的第一电位。 第二开关适于通过响应于使能信号的转换的电路径将逻辑节点连接到第二电位。 数据网络在电气路径内串联连接。 保持电路包括串联连接在逻辑节点和第一电位之间并可彼此独立控制的第三和第四开关，第三开关适于在逻辑节点上的电位呈现第一电位并被打开的情况下被关闭 如果逻辑节点上的电位呈现第二个电位。
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公开(公告)号：US07826299B2
公开(公告)日：2010-11-02
申请号：US12106931
申请日：2008-04-21
申请人： Thomas Kuenemund , Artur Wroblewski
发明人： Thomas Kuenemund , Artur Wroblewski
IPC分类号： G11C8/00
CPC分类号： G11C7/1006 , G11C7/1009
摘要： A plurality of masked memory cells organized in at least two groups, each group using an individual mask signal, is operated by providing a logically valid mask signal only for a selected group comprising the memory cell to be accessed while a logically invalid mask signal are used for all groups other than the selected group.
摘要翻译： 通过在使用逻辑无效掩码信号的情况下，仅为包括要访问的存储器单元的所选择的组提供逻辑有效的掩码信号来操作组中至少两组的每个组的多个屏蔽存储单元，每个组使用单独的屏蔽信号 对于所选组以外的所有组。
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公开(公告)号：US07898836B2
公开(公告)日：2011-03-01
申请号：US12106927
申请日：2008-04-21
申请人： Thomas Kuenemund , Karl Zapf , Artur Wroblewski
发明人： Thomas Kuenemund , Karl Zapf , Artur Wroblewski
IPC分类号： G11C17/00
摘要： An array of masked memory cells including a first memory cell in a first column and a second memory cell in a second different column, wherein the first memory cell is capable of being accessed, so as to output, dependent on a first binary mask signal, a first binary value at a first output and a second binary value at a second output or vice versa, wherein the second memory cell is capable of being accessed, so as to output, dependent on a second binary mask signal, a first binary value at a third output and a second binary value at a fourth output or vice versa, and wherein the second and the third outputs of the memory cells are connected to an identical bit line of the memory array.
摘要翻译： 一种掩蔽存储单元的阵列，包括第一列中的第一存储单元和第二不同列中的第二存储单元，其中第一存储单元能够被访问，以便根据第一二进制掩码信号输出， 在第一输出处的第一二进制值和第二输出处的第二二进制值，反之亦然，其中第二存储器单元能够被访问，以便根据第二二进制掩码信号输出第二二进制值 第三输出和第二二进制值在第四输出或反之亦然，并且其中存储器单元的第二和第三输出连接到存储器阵列的相同位线。
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公开(公告)号：US20090323389A1
公开(公告)日：2009-12-31
申请号：US12106927
申请日：2008-04-21
申请人： THOMAS KUENEMUND , Karl Zapf , Artur Wroblewski
发明人： THOMAS KUENEMUND , Karl Zapf , Artur Wroblewski
摘要： An array of masked memory cells including a first memory cell in a first column and a second memory cell in a second different column, wherein the first memory cell is capable of being accessed, so as to output, dependent on a first binary mask signal, a first binary value at a first output and a second binary value at a second output or vice versa, wherein the second memory cell is capable of being accessed, so as to output, dependent on a second binary mask signal, a first binary value at a third output and a second binary value at a fourth output or vice versa, and wherein the second and the third outputs of the memory cells are connected to an identical bit line of the memory array.
摘要翻译： 一种掩蔽存储单元的阵列，包括第一列中的第一存储单元和第二不同列中的第二存储单元，其中第一存储单元能够被访问，以便根据第一二进制掩码信号输出， 在第一输出处的第一二进制值和第二输出处的第二二进制值，反之亦然，其中第二存储器单元能够被访问，以便根据第二二进制掩码信号输出第二二进制值 第三输出和第二二进制值在第四输出或反之亦然，并且其中存储器单元的第二和第三输出连接到存储器阵列的相同位线。
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