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公开(公告)号：US07003432B2
公开(公告)日：2006-02-21
申请号：US10749460
申请日：2003-12-30
CPC分类号： G11C29/56 , G11C29/56008 , G11C2029/5604
摘要： A method of analyzing cells of a memory device is disclosed. Generally, a plurality of fail signatures is generated, wherein each fail signature is associated with a type of failure. Voltages according to a plurality of test patterns are applied to nodes of a cell of the memory device. Fail data of the cell for the plurality of patterns is then analyzed, and a fail signature of the cell is determined. A type of failure of the cell based upon the plurality of fail signatures is then determined. A system for analyzing cells of a memory device is also disclosed. The system generally includes a plurality of probes applying different voltages to a cell of the memory device. A control circuit varies the voltages applied to the cell, and compares the failures of the cell as the test voltage applied to the cell is varied to an artificial bit map. Finally, an output device generates an output indicating a type of failure of the cell.
摘要翻译： 公开了一种分析存储器件的单元的方法。 通常，生成多个故障签名，其中每个故障签名与一种故障相关联。 根据多个测试图案的电压被施加到存储器件的单元的节点。 然后分析多个模式的单元的失败数据，并且确定单元的失败签名。 然后确定基于多个失败签名的小区的一种故障。 还公开了一种用于分析存储器件单元的系统。 该系统通常包括向存储器件的单元施加不同电压的多个探针。 控制电路改变施加到单元的电压，并且当施加到单元的测试电压变化到人造位图时，比较单元的故障。 最后，输出设备生成指示单元故障类型的输出。
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公开(公告)号：US20050149285A1
公开(公告)日：2005-07-07
申请号：US10749460
申请日：2003-12-30
CPC分类号： G11C29/56 , G11C29/56008 , G11C2029/5604
摘要： A method of analyzing cells of a memory device is disclosed. The method generally comprises steps of establishing a plurality of fail signatures, wherein each fail signature is associated with a type of failure. Voltages according to a plurality of test patterns are applied to nodes of a cell of the memory device. Fail data of the cell for the plurality of patterns is then analyzed, and a fail signature of the cell is determined. A type of failure of the cell based upon the plurality of fail signatures is then determined. A system for analyzing cells of a memory device is also disclosed. The system preferably comprises a plurality of probes applying different voltages to a cell of the memory device. A control circuit varies the voltages applied to the cell, and compares the failures of the cell as the test voltage applied to the cell is varied to an artificial bit map. Finally, an output device generates an output indicating a type of failure of the cell.
摘要翻译： 公开了一种分析存储器件的单元的方法。 该方法通常包括建立多个失败签名的步骤，其中每个故障签名与一种故障相关联。 根据多个测试图案的电压被施加到存储器件的单元的节点。 然后分析多个模式的单元的失败数据，并且确定单元的失败签名。 然后确定基于多个失败签名的小区的一种故障。 还公开了一种用于分析存储器件单元的系统。 该系统优选地包括对存储器件的单元施加不同电压的多个探针。 控制电路改变施加到单元的电压，并且当施加到单元的测试电压变化到人造位图时，比较单元的故障。 最后，输出设备生成指示单元故障类型的输出。
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