GPU Pipeline Multiple Level Synchronization Controller Processor and Method
    1.
    发明申请
    GPU Pipeline Multiple Level Synchronization Controller Processor and Method 有权
    GPU管道多级同步控制器处理器和方法

    公开(公告)号:US20070091102A1

    公开(公告)日:2007-04-26

    申请号:US11552693

    申请日:2006-10-25

    IPC分类号: G06T1/20

    摘要: A method for high level synchronization between an application and a graphics pipeline comprises receiving an application instruction in an input stream at a predetermined component, such as a command stream processor (CSP), as sent by a central processing unit. The CSP may have a first portion coupled to a next component in the graphics pipeline and a second portion coupled to a plurality of components of the graphics pipeline. A command associated with the application instruction may be forwarded from the first portion to the next component in the graphics pipeline or some other component coupled thereto. The command may be received and thereafter executed. A response may be communicated on a feedback path to the second portion of the CSP. Nonlimiting exemplary application instructions that may be received and executed by the CSP include check surface fault, trap, wait, signal, stall, flip, and trigger.

    摘要翻译: 一种用于应用程序和图形流水线之间的高级别同步的方法包括:在由中央处理单元发送的诸如命令流处理器(CSP)的预定组件的输入流中接收应用程序指令。 CSP可以具有耦合到图形流水线中的下一个组件的第一部分和耦合到图形流水线的多个组件的第二部分。 与应用指令相关联的命令可以从第一部分转发到图形流水线中的下一个组件或与其耦合的一些其它组件。 该命令可以被接收并且此后被执行。 响应可以在反馈路径上传送到CSP的第二部分。 可以由CSP接收和执行的非限制性示例性应用指令包括检查表面故障,陷阱,等待,信号,失速,翻转和触发。

    GPU pipeline synchronization and control system and method
    2.
    发明授权
    GPU pipeline synchronization and control system and method 有权
    GPU流水线同步控制系统及方法

    公开(公告)号:US08817029B2

    公开(公告)日:2014-08-26

    申请号:US11468435

    申请日:2006-08-30

    摘要: A graphics pipeline configured to synchronize data processing according to signals and tokens has at least four components. The first component has one input and one output and communicates output tokens or wire signals after receiving tokens on the input, an internal event occurrence, or receipt of a signal on an input path. The second component has one input and a plurality of outputs and communicates tokens or wire signals on one of the outputs after receiving tokens on the input, an internal event occurrence, or receipt of a signal on an input path. The third component has a plurality of inputs and one output and communicates tokens or wire signals on the output after receiving tokens on one of the inputs, an internal event occurrence, or receipt of a signal on an input path. The fourth component has a plurality of inputs and a plurality of outputs and has the capabilities of both the third and forth components.

    摘要翻译: 配置为根据信号和令牌同步数据处理的图形管线具有至少四个组件。 第一个组件具有一个输入和一个输出,并且在接收输入上的令牌,内部事件发生或输入路径上的信号接收之后传送输出令牌或有线信号。 第二分量具有一个输入和多个输出,并且在输入上接收令牌,内部事件发生或输入路径上的信号接收之后,在输出之一上传送令牌或有线信号。 第三组件具有多个输入和一个输出,并且在输入之一上接收令牌,内部事件发生或输入路径上的信号接收之后,在输出端上传送令牌或有线信号。 第四组件具有多个输入和多个输出,并且具有第三和第四组件的能力。

    GPU Pipeline Synchronization and Control System and Method
    3.
    发明申请
    GPU Pipeline Synchronization and Control System and Method 有权
    GPU管线同步与控制系统与方法

    公开(公告)号:US20070091100A1

    公开(公告)日:2007-04-26

    申请号:US11468435

    申请日:2006-08-30

    IPC分类号: G06T1/20

    摘要: A graphics pipeline configured to synchronize data processing according to signals and tokens has at least four components. The first component has one input and one output and communicates output tokens or wire signals after receiving tokens on the input, an internal event occurrence, or receipt of a signal on an input path. The second component has one input and a plurality of outputs and communicates tokens or wire signals on one of the outputs after receiving tokens on the input, an internal event occurrence, or receipt of a signal on an input path. The third component has a plurality of inputs and one output and communicates tokens or wire signals on the output after receiving tokens on one of the inputs, an internal event occurrence, or receipt of a signal on an input path. The fourth component has a plurality of inputs and a plurality of outputs and has the capabilities of both the third and forth components.

    摘要翻译: 配置为根据信号和令牌同步数据处理的图形管线具有至少四个组件。 第一个组件具有一个输入和一个输出,并且在接收输入上的令牌,内部事件发生或输入路径上的信号接收之后传送输出令牌或有线信号。 第二分量具有一个输入和多个输出,并且在输入上接收令牌,内部事件发生或输入路径上的信号接收之后,在输出之一上传送令牌或有线信号。 第三组件具有多个输入和一个输出,并且在输入之一上接收令牌,内部事件发生或输入路径上的信号接收之后,在输出端上传送令牌或有线信号。 第四组件具有多个输入和多个输出,并且具有第三和第四组件的能力。

    Color compression using an edge data bitmask in a multi-sample anti-aliasing scheme
    4.
    发明申请
    Color compression using an edge data bitmask in a multi-sample anti-aliasing scheme 审中-公开
    使用多样本抗锯齿方案中的边缘数据位掩码进行颜色压缩

    公开(公告)号:US20060170703A1

    公开(公告)日:2006-08-03

    申请号:US11047904

    申请日:2005-02-01

    申请人: Qunfeng Liao

    发明人: Qunfeng Liao

    IPC分类号: G09G5/00

    摘要: Systems and methods are provided for compressing computer graphics color data in a system utilizing a multi-sample anti-aliasing scheme using an edge data bitmask to generate a compression code for determining the compressibility of tile color data, where the edge data bitmask is a record of edge locations relative to the pixels and sub-pixels within a tile.

    摘要翻译: 提供了系统和方法,用于使用边缘数据位掩码的多样本抗混叠方案来压缩系统中的计算机图形颜色数据,以生成用于确定瓦片颜色数据的可压缩性的压缩码,其中边缘数据位掩码是记录 的边缘位置相对于瓦片内的像素和子像素。