公开(公告)号：US07298777B2

公开(公告)日：2007-11-20

申请号：US10455020

申请日：2003-06-06

申请人： John G. McDonough ,  Gibong Jeong ,  Karim Abdulla ,  Rajiv R. Nambiar ,  William S. Clark, Jr.

发明人： John G. McDonough ,  Gibong Jeong ,  Karim Abdulla ,  Rajiv R. Nambiar ,  William S. Clark, Jr.

IPC分类号： H04B1/00

CPC分类号： H04B1/708

摘要： This disclosure is generally directed to communication systems, devices used in communication systems and associated methods which may implement parallel hypothesis search techniques. The disclosed parallel hypothesis search techniques may permit a hypothesis to be dismissed early (i.e., before hypotheses in other searchers have completed their evaluation). Early hypothesis dismissal permits a new hypothesis to be loaded into the searcher while other searchers advantageously continue to evaluate their hypotheses.

摘要翻译： 本公开通常涉及通信系统，在通信系统中使用的设备和可以实现并行假设搜索技术的相关方法。 公开的平行假设检索技术可以允许早期解除假设（即，在其他搜索者的假设已经完成其评估之前）。 早期假设解雇允许将新假设加载到搜索者中，而其他搜索者有利地继续评估其假设。

公开(公告)号：US07295598B2

公开(公告)日：2007-11-13

申请号：US10439400

申请日：2003-05-16

申请人： John G. McDonough ,  Gibong Jeong ,  Karim Abdulla ,  Rajiv R. Nambiar ,  William S. Clark, Jr.

发明人： John G. McDonough ,  Gibong Jeong ,  Karim Abdulla ,  Rajiv R. Nambiar ,  William S. Clark, Jr.

IPC分类号： H04B1/00

CPC分类号： H04B1/70755

摘要： A method and system for processing the results of searches for signals in a direct sequence spread spectrum communications system in an intelligent and efficient manner. A preferred embodiment comprises a search engine (for example, search engine 405) and a hardware result processor (for example, result processor 410) with a memory (for example, memory 415) as an interface. The search engine may perform multiple correlations of a pilot channel and then writes the correlation results exceeding a specified threshold to the memory. The result processor reads the correlation results from the memory and performs result filtering and builds a list of maximum value correlation results. The result processor and the search engine functions with independence from one another therefore, there is therefore, little wasted overhead where one has to wait for the other. The result filtering also makes it simpler to combine signal multipaths and simplifies pilot channel strength comparisons.

摘要翻译： 一种用于以智能且有效的方式处理在直接序列扩频通信系统中搜索信号的结果的方法和系统。 优选实施例包括具有作为接口的存储器（例如，存储器415）的搜索引擎（例如，搜索引擎405）和硬件结果处理器（例如，结果处理器410）。 搜索引擎可以执行导频信道的多个相关性，然后将超过规定阈值的相关结果写入存储器。 结果处理器从存储器读取相关结果，并执行结果过滤，并建立最大值相关结果列表。 结果处理器和搜索引擎的功能彼此独立，因此，因此，必须等待另一个的开销很少。 结果滤波也使得组合信号多路径更简单，并简化了导频信道强度比较。

公开(公告)号：US4672613A

公开(公告)日：1987-06-09

申请号：US794070

申请日：1985-11-01

申请人： Neal E. Foxworthy ,  William S. Clark, Jr. ,  Stephen R. Schossow ,  Robert J. Gabbay

发明人： Neal E. Foxworthy ,  William S. Clark, Jr. ,  Stephen R. Schossow ,  Robert J. Gabbay

IPC分类号： G06F13/00 ,  G06F3/06 ,  G06F11/10 ,  G06F13/12 ,  G06F13/28

CPC分类号： G06F3/0601 ,  G06F11/10 ,  G06F13/28 ,  G06F2003/0691

摘要： In a system for transferring data between a host device and a target recording medium, a buffer interface control unit includes a host direct memory access (DMA) unit for transferring data from the host unit to a buffer memory. The host DMA unit accesses a first set of prescribed noncontinuous buffer memory storage locations to store the data transferred from the host unit in a predetermined buffer format that includes additional sets of prescribed storage locations interspersed with the first set of data storage locations for the storage of error code characters pertaining to the data. The host DMA unit also transfers error correction code characters pertaining to the data to one of the additional sets of prescribed storage locations. The buffer interface control unit further includes a target DMA unit for transferring data from the buffer memory to a write interface unit. The target DMA unit accesses the buffer memory storage locations in a predetermined noncontinuous sequence in order to retrieve the data from the buffer memory in a format that includes open time slots interspersed with time slots occupied by the retrieved data for the insertion of error detection code characters pertaining to the data retrieved from the buffer memory.

摘要翻译： 在用于在主机设备和目标记录介质之间传送数据的系统中，缓冲器接口控制单元包括用于将数据从主机单元传送到缓冲存储器的主机直接存储器访问（DMA）单元。 主机DMA单元访问第一组规定的非连续缓冲存储器存储位置，以以预定的缓冲器格式存储从主机单元传送的数据，该预定缓冲器格式包括与第一组数据存储位置分开的额外的规定存储位置集合，用于存储 与数据有关的错误代码字符。 主机DMA单元还将与数据相关的纠错码字符传送到附加的一组规定的存储位置中的一个。 缓冲器接口控制单元还包括用于将数据从缓冲存储器传送到写入接口单元的目标DMA单元。 目标DMA单元以预定的非连续序列访问缓冲存储器存储位置，以便以包括用于插入错误检测码字符的检索数据所占用的时隙散布的开放时隙的格式从缓冲存储器检索数据 属于从缓冲存储器检索的数据。