公开(公告)号：US6067327A

公开(公告)日：2000-05-23

申请号：US933192

申请日：1997-09-18

申请人： John Lock Creigh ,  Michel Ferry ,  Thomas Ashford Hughes, Jr. ,  Scott David Huss

发明人： John Lock Creigh ,  Michel Ferry ,  Thomas Ashford Hughes, Jr. ,  Scott David Huss

IPC分类号： H03M1/66 ,  H04L25/49

CPC分类号： H03M1/661

摘要： A data transmitter is provided which performs digital to analog conversion, convolution with an arbitrary finite impulse response, and smoothing of the output functions without requiring a separate anti-aliasing low pass filter. To implement the data transmitter, a digital input data value is convolved with a desired impulse response. The coefficients of the desired finite impulse response filter are chosen to create a first or second derivative of an output of the data transmitter. Then, the derivative is integrated so that a resulting signal output from the data transmitter is a smooth signal which does not require further filtering.

摘要翻译： 提供了一种数据发射器，其执行数字到模拟转换，与任意有限脉冲响应卷积，以及输出功能的平滑，而不需要单独的抗混叠低通滤波器。 为了实现数据发送器，数字输入数据值与期望的脉冲响应进行卷积。 选择期望的有限脉冲响应滤波器的系数以产生数据发射机的输出的第一或第二导数。 然后，导数被积分，使得从数据发射器输出的结果信号是不需要进一步滤波的平滑信号。

公开(公告)号：US07460840B2

公开(公告)日：2008-12-02

申请号：US11022854

申请日：2004-12-28

申请人： John Lock Creigh

发明人： John Lock Creigh

IPC分类号： H04B17/00

CPC分类号： H04B17/20 ,  H04B17/15

摘要： A multi-port transceiver includes a transmitter and receiver for each port. The invention is a test method and apparatus for testing individual components in the transmit and receive paths. Specifically, the invention includes a method of testing the full range of a programmable gain amplifier (PGA) and an analog to digital converter (ADC) in the receive path of each port. This is accomplished by connecting the transmitter of one port directly to the receiver of a second port, and varying the amplitude of the transmitter over a range of gain settings of the PGA while examining if the dynamic range of the receiver has been exceeded.

摘要翻译： 多端口收发器包括每个端口的发送器和接收器。 本发明是用于测试发送和接收路径中的各个组件的测试方法和装置。 具体地，本发明包括一种在每个端口的接收路径中测试可编程增益放大器（PGA）和模数转换器（ADC）的全范围的方法。 这通过将一个端口的发射机直接连接到第二端口的接收机来实现，并且在PGA的增益设置的范围内改变发射机的幅度，同时检查接收机的动态范围是否已被超过。

公开(公告)号：US07350121B2

公开(公告)日：2008-03-25

申请号：US11203288

申请日：2005-08-15

申请人： John Lock Creigh

发明人： John Lock Creigh

IPC分类号： G01R31/28

CPC分类号： G01R31/3177

摘要： A logic analyzer having internal access to the test buses, clocks and events of a chip is used to debug the chip. The logic analyzer is designed with the capability to share existing memory in the chip during the debug process. Additionally, the configuration of the logic analyzer and observation of the acquired results in the shared memory can be accessed through normal control interfaces of the chip and does not require special test cards. The logic analyzer includes a clocking function, a trigger function, a signal multiplexer, and a memory block. The clocking function is configured to select as the sample clock for the function any of the clocks in the integrated circuit. In addition, the clocking function may provide a means to decimate these clocks by some factor to sample over larger intervals.

摘要翻译： 使用具有对测试总线，芯片的时钟和事件的内部访问的逻辑分析器来调试芯片。 逻辑分析仪的设计能够在调试过程中共享芯片中的现有存储器。 此外，可以通过芯片的正常控制接口访问逻辑分析器的配置和获取的结果在共享存储器中的观察，并且不需要特殊的测试卡。 逻辑分析仪包括时钟功能，触发功能，信号多路复用器和存储块。 时钟功能配置为选择集成电路中任何时钟功能的采样时钟。 此外，时钟功能可以提供通过一些因素来抽取这些时钟的装置，以在较大间隔上采样。

公开(公告)号：US08514951B2

公开(公告)日：2013-08-20

申请号：US12857303

申请日：2010-08-16

申请人： Mehdi Tavassoli Kilani ,  Scott Powell ,  Kadir Dinc ,  Kishore Kota ,  John Lock Creigh ,  Hooman Parizi

发明人： Mehdi Tavassoli Kilani ,  Scott Powell ,  Kadir Dinc ,  Kishore Kota ,  John Lock Creigh ,  Hooman Parizi

IPC分类号： H04L1/00

CPC分类号： H04B1/10 ,  H04L25/0274 ,  H04L25/0292 ,  H04L25/085

摘要： Aspects of a method and system for interference cancellation substantially as shown in and/or described in connection with at least one of the figures, as set forth more completely in the claims. In this regard, a receiver may be operable to receive a differential signal via a differential channel, and to sense a common mode signal on the differential channel. A frequency range in which interference is present in the common mode signal may be determined. The differential signal and the common mode signal may be filtered to attenuate frequencies outside the determined frequency range. A phase and/or amplitude of the filtered common mode signal may be adjusted based on the filtered differential signal and the adjusted and filtered common mode signal may be subtracted from the received differential signal. The common mode signal may be sensed via a pair of resistors coupled to the differential channel.

公开(公告)号：US5956348A

公开(公告)日：1999-09-21

申请号：US826845

申请日：1997-04-08

申请人： John Lock Creigh ,  Francis E. Noel, Jr. ,  Lorrie A. Tomek

发明人： John Lock Creigh ,  Francis E. Noel, Jr. ,  Lorrie A. Tomek

IPC分类号： H04L12/56 ,  H04Q11/04 ,  H04J3/12 ,  H04J3/06

CPC分类号： H04Q11/0478 ,  H04L2012/5615

摘要： Variable length LAN frames can be segmented into fixed length cells to allow the data in the frames to be transported through an intermediate cell-based system, such as an ATM network. Where transport through the intermediate system results in time gaps between data units extracted from the cells, special symbol combinations can be inserted into the time gaps to permit frame-representing data to be forwarded toward its destination as a "stretched frame" without waiting for all the cells representing the frame to arrive. When a stretched LAN frame is received at a "stretch-aware" LAN station, the special symbol combinations are detected and removed to recover at least the data payload of the original LAN frame.

摘要翻译： 可变长度的LAN帧可以被分割成固定长度的小区，以允许帧中的数据通过诸如ATM网络的基于中间小区的系统传送。 在通过中间系统的传输导致从小区提取的数据单元之间的时间间隔时，可以将特殊符号组合插入到时间间隙中，以允许帧表示数据作为“延伸帧”转发到其目的地而不等待所有 表示框架的单元即将到达。 当在“伸展感知”LAN站处接收到拉伸的LAN帧时，检测和去除特殊符号组合以至少恢复原始LAN帧的数据有效载荷。