Architecture and Instructions for Accessing Multi-Dimensional Formatted Surface Memory
    1.
    发明申请
    Architecture and Instructions for Accessing Multi-Dimensional Formatted Surface Memory 有权
    用于访问多维格式化表面存储器的体系结构和说明

    公开(公告)号:US20110074802A1

    公开(公告)日:2011-03-31

    申请号:US12890171

    申请日:2010-09-24

    IPC分类号: G06F12/00

    CPC分类号: G06T1/60

    摘要: One embodiment of the present invention sets forth a technique for a program to access multi-dimensional formatted graphics surface memory. Multi-dimensional memory objects called “surfaces” stored in a user-specified data or pixel format and arranged in a graphics optimized layout are accessed by programs using surface instructions. A set of memory access instructions e.g., load, store, reduce, and atomic, referred to as surface instructions, may be used to access the surfaces. Coordinate bounds checking is performed with configurable clamping. Caching behavior may also be specified by the surface instructions. Data format conversion and packing to a specified storage format is supported for store, reduction, and atomic surface instructions. Data format conversion and unpacking from a specified storage format is supported for loads and atomic surface instructions.

    摘要翻译: 本发明的一个实施例提出了一种用于访问多维格式化图形表面存储器的程序的技术。 称为“表面”的多维存储器对象以用户指定的数据或像素格式存储并以图形优化的布局布置,由使用表面指令的程序访问。 可以使用一组存储器访问指令,例如加载,存储,减少和原子,称为表面指令,以访问表面。 通过可配置的夹紧进行坐标界限检查。 缓存行为也可以由表面指令指定。 支持存储,缩小和原子表面指令的数据格式转换和打包到指定的存储格式。 负载和原子表面指令支持从指定的存储格式进行数据格式转换和解包。

    Architecture and instructions for accessing multi-dimensional formatted surface memory
    2.
    发明授权
    Architecture and instructions for accessing multi-dimensional formatted surface memory 有权
    用于访问多维格式化表面存储器的体系结构和指令

    公开(公告)号:US09519947B2

    公开(公告)日:2016-12-13

    申请号:US12890171

    申请日:2010-09-24

    IPC分类号: G06F12/00 G06T1/60

    CPC分类号: G06T1/60

    摘要: One embodiment of the present invention sets forth a technique for a program to access multi-dimensional formatted graphics surface memory. Multi-dimensional memory objects called “surfaces” stored in a user-specified data or pixel format and arranged in a graphics optimized layout are accessed by programs using surface instructions. A set of memory access instructions e.g., load, store, reduce, and atomic, referred to as surface instructions, may be used to access the surfaces. Coordinate bounds checking is performed with configurable clamping. Caching behavior may also be specified by the surface instructions. Data format conversion and packing to a specified storage format is supported for store, reduction, and atomic surface instructions. Data format conversion and unpacking from a specified storage format is supported for loads and atomic surface instructions.

    摘要翻译: 本发明的一个实施例提出了一种用于访问多维格式化图形表面存储器的程序的技术。 称为“表面”的多维存储器对象以用户指定的数据或像素格式存储并以图形优化的布局布置,由使用表面指令的程序访问。 可以使用一组存储器访问指令,例如加载,存储,减少和原子,称为表面指令,以访问表面。 通过可配置的夹紧进行坐标界限检查。 缓存行为也可以由表面指令指定。 支持存储,缩小和原子表面指令的数据格式转换和打包到指定的存储格式。 负载和原子表面指令支持从指定的存储格式进行数据格式转换和解包。

    Cooperative thread array reduction and scan operations
    7.
    发明授权
    Cooperative thread array reduction and scan operations 有权
    合作线程数组减少和扫描操作

    公开(公告)号:US08539204B2

    公开(公告)日:2013-09-17

    申请号:US12890227

    申请日:2010-09-24

    IPC分类号: G06F9/30 G06F9/40 G06F15/00

    摘要: One embodiment of the present invention sets forth a technique for performing aggregation operations across multiple threads that execute independently. Aggregation is specified as part of a barrier synchronization or barrier arrival instruction, where in addition to performing the barrier synchronization or arrival, the instruction aggregates (using reduction or scan operations) values supplied by each thread. When a thread executes the barrier aggregation instruction the thread contributes to a scan or reduction result, and waits to execute any more instructions until after all of the threads have executed the barrier aggregation instruction. A reduction result is communicated to each thread after all of the threads have executed the barrier aggregation instruction and a scan result is communicated to each thread as the barrier aggregation instruction is executed by the thread.

    摘要翻译: 本发明的一个实施例提出了一种用于跨独立执行的多个线程执行聚合操作的技术。 聚合被指定为屏障同步或屏障到达指令的一部分,其中除了执行屏障同步或到达之外,指令聚合(使用缩减或扫描操作)由每个线程提供的值。 当线程执行屏障聚合指令时,线程有助于扫描或缩小结果,并等待执行任何更多指令,直到所有线程都执行了阻挡聚合指令为止。 在所有线程执行了屏障聚合指令之后,向每个线程传送减少结果,并且当线程执行屏障聚合指令时,将扫描结果传送给每个线程。

    COOPERATIVE THREAD ARRAY REDUCTION AND SCAN OPERATIONS
    10.
    发明申请
    COOPERATIVE THREAD ARRAY REDUCTION AND SCAN OPERATIONS 有权
    合作螺线减排和扫描作业

    公开(公告)号:US20110078417A1

    公开(公告)日:2011-03-31

    申请号:US12890227

    申请日:2010-09-24

    IPC分类号: G06F9/38

    摘要: One embodiment of the present invention sets forth a technique for performing aggregation operations across multiple threads that execute independently. Aggregation is specified as part of a barrier synchronization or barrier arrival instruction, where in addition to performing the barrier synchronization or arrival, the instruction aggregates (using reduction or scan operations) values supplied by each thread. When a thread executes the barrier aggregation instruction the thread contributes to a scan or reduction result, and waits to execute any more instructions until after all of the threads have executed the barrier aggregation instruction. A reduction result is communicated to each thread after all of the threads have executed the barrier aggregation instruction and a scan result is communicated to each thread as the barrier aggregation instruction is executed by the thread.

    摘要翻译: 本发明的一个实施例提出了一种用于跨独立执行的多个线程执行聚合操作的技术。 聚合被指定为屏障同步或屏障到达指令的一部分,其中除了执行屏障同步或到达之外,指令聚合(使用缩减或扫描操作)由每个线程提供的值。 当线程执行屏障聚合指令时,线程有助于扫描或缩小结果,并等待执行任何更多指令,直到所有线程都执行了阻挡聚合指令为止。 在所有线程执行了屏障聚合指令之后,向每个线程传送减少结果,并且当线程执行屏障聚合指令时,将扫描结果传送给每个线程。