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公开(公告)号：US08659694B2
公开(公告)日：2014-02-25
申请号：US12953535
申请日：2010-11-24
CPC分类号： H04N5/3658 , H04N5/341 , H04N5/3577 , H04N5/3742 , H04N5/3765
摘要： An image sensor includes a two-dimensional array of pixels having multiple column outputs and an output circuit connected to each column output. Each output circuit is configured to operate concurrent sample and read operations. An analog front end (AFE) circuit processes pixel data output from the output circuits and an AFE clock controller transmits an AFE clocking signal to the AFE circuit to effect processing of the pixel data. A timing generator outputs a column address sequence that is received by a column decoder. During one or more sample operations the timing generator suspends the column address sequence and subsequently during the one or more sample operations the AFE clock controller suspends the AFE clocking signal. The AFE clocking signal and the column address sequence resume at the end of the one or more sample operations.
摘要翻译： 图像传感器包括具有多个列输出的像素的二维阵列和连接到每个列输出的输出电路。 每个输出电路配置为同时进行采样和读取操作。 模拟前端（AFE）电路处理从输出电路输出的像素数据，AFE时钟控制器将AFE时钟信号发送到AFE电路以实现像素数据的处理。 定时发生器输出由列解码器接收的列地址序列。 在一个或多个采样操作期间，定时发生器暂停列地址序列，随后在一个或多个采样操作期间，AFE时钟控制器暂停AFE计时信号。 AFE计时信号和列地址序列在一个或多个采样操作结束时恢复。
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公开(公告)号：US20120154653A1
公开(公告)日：2012-06-21
申请号：US12972964
申请日：2010-12-20
IPC分类号： H04N5/335
CPC分类号： H04N5/3765 , H04N5/3658 , H04N5/3742
摘要： An image sensor includes a two-dimensional array of pixels having multiple column outputs and an output circuit connected to each column output. Each output circuit is configured to operate concurrent sample and read operations. A timing generator outputs a column address sequence that is received by a column decoder that is electrically connected to each output circuit. The timing generator suspends the output of the column address sequence during a sample operation and resumes the output of the column address sequence at the end of the sample operation.
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公开(公告)号：US20120154655A1
公开(公告)日：2012-06-21
申请号：US12972947
申请日：2010-12-20
IPC分类号： H04N5/335
CPC分类号： H04N5/3742 , H04N5/3658 , H04N5/3765
摘要： An image sensor includes a two-dimensional array of pixels having multiple column outputs and an output circuit connected to each column output. Each output circuit is configured to operate concurrent sample and read operations. A timing generator outputs a column address sequence that is received by a column decoder that is electrically connected to each output circuit. The timing generator suspends the output of the column address sequence during a sample operation and resumes the output of the column address sequence at the end of the sample operation.
摘要翻译： 图像传感器包括具有多个列输出的像素的二维阵列和连接到每个列输出的输出电路。 每个输出电路配置为同时进行采样和读取操作。 定时发生器输出由与每个输出电路电连接的列解码器接收的列地址序列。 定时发生器在采样操作期间暂停列地址序列的输出，并在采样操作结束时恢复列地址序列的输出。
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公开(公告)号：US08384813B2
公开(公告)日：2013-02-26
申请号：US12972947
申请日：2010-12-20
CPC分类号： H04N5/3742 , H04N5/3658 , H04N5/3765
摘要： An image sensor includes a two-dimensional array of pixels having multiple column outputs and an output circuit connected to each column output. Each output circuit is configured to operate concurrent sample and read operations. A timing generator outputs a column address sequence that is received by a column decoder that is electrically connected to each output circuit. The timing generator suspends the output of the column address sequence during a sample operation and resumes the output of the column address sequence at the end of the sample operation.
摘要翻译： 图像传感器包括具有多个列输出的像素的二维阵列和连接到每个列输出的输出电路。 每个输出电路配置为同时进行采样和读取操作。 定时发生器输出由与每个输出电路电连接的列解码器接收的列地址序列。 定时发生器在采样操作期间暂停列地址序列的输出，并在采样操作结束时恢复列地址序列的输出。
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公开(公告)号：US20110157438A1
公开(公告)日：2011-06-30
申请号：US12953535
申请日：2010-11-24
IPC分类号： H04N5/335
CPC分类号： H04N5/3658 , H04N5/341 , H04N5/3577 , H04N5/3742 , H04N5/3765
摘要： An image sensor includes a two-dimensional array of pixels having multiple column outputs and an output circuit connected to each column output. Each output circuit is configured to operate concurrent sample and read operations. An analog front end (AFE) circuit processes pixel data output from the output circuits and an AFE clock controller transmits an AFE clocking signal to the AFE circuit to effect processing of the pixel data. A timing generator outputs a column address sequence that is received by a column decoder. During one or more sample operations the timing generator suspends the column address sequence and subsequently during the one or more sample operations the AFE clock controller suspends the AFE clocking signal. The AFE clocking signal and the column address sequence resume at the end of the one or more sample operations.
摘要翻译： 图像传感器包括具有多个列输出的像素的二维阵列和连接到每个列输出的输出电路。 每个输出电路配置为同时进行采样和读取操作。 模拟前端（AFE）电路处理从输出电路输出的像素数据，AFE时钟控制器将AFE时钟信号发送到AFE电路以实现像素数据的处理。 定时发生器输出由列解码器接收的列地址序列。 在一个或多个采样操作期间，定时发生器暂停列地址序列，随后在一个或多个采样操作期间，AFE时钟控制器暂停AFE计时信号。 AFE计时信号和列地址序列在一个或多个采样操作结束时恢复。
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公开(公告)号：US08525910B2
公开(公告)日：2013-09-03
申请号：US12952466
申请日：2010-11-23
CPC分类号： H04N5/3742 , H04N5/3577
摘要： An image sensor includes a two-dimensional array of pixels having multiple column outputs and an output circuit connected to each column output. Each output circuit is configured to operate concurrent sample and read operations. An analog front end (AFE) circuit processes pixel data output from the output circuits and an AFE clock controller transmits an AFE clocking signal to the AFE circuit to effect processing of the pixel data. A timing generator outputs a column address sequence that is received by a column decoder. During one or more sample operations the AFE clock controller suspends the output of the AFE clocking signal and the timing generator suspends the output of the column address sequence during the sample operation. The output of the AFE clocking signal and the column address sequence resume at the end of the sample operation.
摘要翻译： 图像传感器包括具有多个列输出的像素的二维阵列和连接到每个列输出的输出电路。 每个输出电路配置为同时进行采样和读取操作。 模拟前端（AFE）电路处理从输出电路输出的像素数据，AFE时钟控制器将AFE时钟信号发送到AFE电路以实现像素数据的处理。 定时发生器输出由列解码器接收的列地址序列。 在一个或多个采样操作期间，AFE时钟控制器暂停AFE时钟信号的输出，定时发生器在采样操作期间暂停列地址序列的输出。 在样品操作结束时，AFE时钟信号和列地址序列的输出恢复。
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公开(公告)号：US08199225B2
公开(公告)日：2012-06-12
申请号：US12655539
申请日：2009-12-31
IPC分类号： H04N9/64
CPC分类号： H04N5/3658
摘要： An image sensor includes multiple photoactive pixels and multiple dark reference pixels typically arranged in rows and columns to form a pixel array. A dark signal is read out from a given number of dark reference pixels in each column at a first gain level. An initial column offset correction is determined for one or more columns in the pixel array using respective dark signals read out at the first gain level. The initial column offset corrections are repeatedly scaled in response to each detected change to a different gain level. The column offset corrections can be scaled based on an amount of change between each respective different gain level and the first gain level.
摘要翻译： 图像传感器包括多个光活性像素和通常以行和列布置以形成像素阵列的多个暗参考像素。 从第一增益级别的每列中的给定数量的暗参考像素读出暗信号。 使用在第一增益级读出的各个暗信号，确定像素阵列中的一列或多列的初始列偏移校正。 响应于每个检测到的改变到不同的增益水平，重复地缩放初始列偏移校正。 可以基于每个相应的不同增益级别和第一增益级别之间的变化量来对列偏移校正进行缩放。
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公开(公告)号：US20110157444A1
公开(公告)日：2011-06-30
申请号：US12952466
申请日：2010-11-23
IPC分类号： H04N5/335
CPC分类号： H04N5/3742 , H04N5/3577
摘要： An image sensor includes a two-dimensional array of pixels having multiple column outputs and an output circuit connected to each column output. Each output circuit is configured to operate concurrent sample and read operations. An analog front end (AFE) circuit processes pixel data output from the output circuits and an AFE clock controller transmits an AFE clocking signal to the AFE circuit to effect processing of the pixel data. A timing generator outputs a column address sequence that is received by a column decoder. During one or more sample operations the AFE clock controller suspends the output of the AFE clocking signal and the timing generator suspends the output of the column address sequence during the sample operation. The output of the AFE clocking signal and the column address sequence resume at the end of the sample operation.
摘要翻译： 图像传感器包括具有多个列输出的像素的二维阵列和连接到每个列输出的输出电路。 每个输出电路配置为同时进行采样和读取操作。 模拟前端（AFE）电路处理从输出电路输出的像素数据，AFE时钟控制器将AFE时钟信号发送到AFE电路以实现像素数据的处理。 定时发生器输出由列解码器接收的列地址序列。 在一个或多个采样操作期间，AFE时钟控制器暂停AFE时钟信号的输出，定时发生器在采样操作期间暂停列地址序列的输出。 在样品操作结束时，AFE时钟信号和列地址序列的输出恢复。
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公开(公告)号：US20110157433A1
公开(公告)日：2011-06-30
申请号：US12655539
申请日：2009-12-31
IPC分类号： H04N9/64
CPC分类号： H04N5/3658
摘要： An image sensor includes multiple photoactive pixels and multiple dark reference pixels typically arranged in rows and columns to form a pixel array. A dark signal is read out from a given number of dark reference pixels in each column at a first gain level. An initial column offset correction is determined for one or more columns in the pixel array using respective dark signals read out at the first gain level. The initial column offset corrections are repeatedly scaled in response to each detected change to a different gain level. The column offset corrections can be scaled based on an amount of change between each respective different gain level and the first gain level.
摘要翻译： 图像传感器包括多个光活性像素和通常以行和列布置以形成像素阵列的多个暗参考像素。 从第一增益级别的每列中的给定数量的暗参考像素读出暗信号。 使用在第一增益级读出的各个暗信号，确定像素阵列中的一列或多列的初始列偏移校正。 响应于每个检测到的改变到不同的增益水平，重复地缩放初始列偏移校正。 可以基于每个相应的不同增益级别和第一增益级别之间的变化量来对列偏移校正进行缩放。
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公开(公告)号：US20110157434A1
公开(公告)日：2011-06-30
申请号：US12655559
申请日：2009-12-31
IPC分类号： H04N5/217
CPC分类号： H04N5/3658
摘要： An image sensor includes multiple photoactive pixels and multiple dark reference pixels arranged in rows and columns to form a pixel array. A dark signal is read out of one or more dark reference pixels in each column and used to determine a column offset for one or more columns in the pixel array. Each time an image or frame of an image is read out, the column offset for the one or more columns is updated using dark signals read out from a given number of dark reference pixels. The column offset for the one or more columns is scaled when a gain level is changed for a captured image.
摘要翻译： 图像传感器包括以行和列排列以形成像素阵列的多个光活性像素和多个暗参考像素。 从每列中的一个或多个暗参考像素中读出暗信号，并用于确定像素阵列中的一个或多个列的列偏移。 每次读出图像的图像或帧时，使用从给定数量的暗参考像素读出的暗信号来更新一列或多列的列偏移。 当为捕获的图像改变增益级别时，对一个或多个列的列偏移进行缩放。
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